Arm Enables Custom Instructions for Embedded CPUs

October 09, 2019

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Arm Enables Custom Instructions for Embedded CPUs

Arm CEO Simon Segars announced Arm Custom Instructions, a new feature for the Armv8-M architecture at Arm TechCon 2019.

• Arm Custom Instructions enable partners designing SoCs to differentiate through optimization for specific embedded and IoT applications

• Architected to support intelligent and rapid development of fully integrated custom CPU instructions without software fragmentation

• Builds on key benefits of Armv8-M architecture including a strong software ecosystem, security and greater processing acceleration – with no additional costs

SAN JOSE, Calif.--()--Arm TechCon – Today at Arm TechCon 2019, Arm CEO Simon Segars announced Arm Custom Instructions, a new feature for the Armv8-M architecture. Arm Custom Instructions will initially be implemented in Arm Cortex®-M33 CPUs starting in the first half of 2020 at no additional cost to new and existing licensees, enabling SoC designers to add their own instructions for specific embedded and IoT applications without risk of software fragmentation.

Arm Enables Custom Instructions for Embedded CPUs

“A world of a trillion secure intelligent devices will be built on a diversity of complex use cases requiring increased synergy between hardware and software design,” said Dipti Vachani, senior vice president and general manager, Automotive and IoT Line of Business, Arm. “We have engineered Arm Custom Instructions to fuel closer hardware and software co-design efforts toward achieving application-specific acceleration while unlocking greater device differentiation.”

The CPU: A chassis for Arm silicon partner innovation

Architected as part of the evolution of the Armv8-M architecture with secure Arm TrustZone™ technology, Arm Custom Instructions are based on a simple guiding principle; the CPU is a chassis for Arm silicon partner innovation. This approach gives chip designers the opportunity to push performance and efficiency further by adding their unique application-specific features into Cortex-M33 CPUs.

Arm Custom Instructions are enabled by modifications to the CPU that reserve encoding space for designers to easily add custom datapath extensions while maintaining the integrity of the existing software ecosystem. This feature, together with the existing coprocessor interface, enable Cortex-M33 CPUs to be extended with various types of accelerators optimized for edge compute use cases including machine learning (ML) and artificial intelligence (AI).

More technical details on Arm Custom Instructions can be found here.

Greater ecosystem flexibility and differentiation

Arm Custom Instructions, combined with the recent introduction of Arm Flexible Access, underscore Arm’s increased commitment to enhance silicon partner flexibility and differentiation in support of new edge computing opportunities in ML, AI, self-driving cars, 5G and IoT. Further strengthening this commitment, Arm will offer Custom Instructions as a standard feature in future Cortex-M CPUs, which are among the most successful Arm CPUs ever, having shipped in more than 50 billion chips from Arm silicon partners to-date.

Partner quotes:

“SoC vendors often need optimized tools to extend the capabilities of their designs without compromising on safety, security or the existing development tools investments such as IAR Embedded Workbench. Arm Custom Instructions provides them with a simple, but powerful mechanism for addressing their unique requirements while maintaining the integrity and efficiency of the processes already in place.”

Stefan Skarin, president and CEO, IAR Systems AB

“Arm’s new Custom Instructions capabilities allow silicon suppliers like NXP to offer their customers a new degree of application-specific instruction optimizations to improve performance, power dissipation and static code size for new and emerging embedded applications. Additionally, all these improvements are enabled within the extensive Cortex-M ecosystem, so customers’ existing software investments are maximized.”

Geoff Lees, SVP and GM of Microcontrollers at NXP®Semiconductors

"The world of one trillion securely connected devices poses several challenges to silicon designers due to the expanding demand for extremely energy-efficient devices. The introduction of Arm Custom Instructions in the Cortex-M portfolio will enable Silicon Labs to design systems uniquely optimized for specific tasks within a wide range of connected IoT devices.”

Alessandro Piovaccari, chief technology officer, Silicon Labs

"ST's STM32 Arm-based microcontrollers are already at the heart of millions of smart objects in industrial, consumer and medical markets. The relentless demand for ever greater performance, power efficiency and security require an evolution of the design approach where hardware is designed alongside software from the beginning. With Arm Custom Instructions in future Armv8-M cores, Arm is enabling hardware/software co-design. This will in turn enable ST to bring additional differentiation and value to the next generation of IoT devices designed by our customers with the STM32 hardware, software and tools ecosystem, with features including optimized security and signal processing at core level.”

Ricardo De Sa Earp, general manager of STMicroelectronics’ Microcontroller Division

About Arm

Arm technology is at the heart of a computing and connectivity revolution that is transforming the way people live and businesses operate. Our advanced, energy-efficient processor designs have enabled intelligent computing in more than 150 billion chips. More than 70% of the world’s population are using Arm technology, which is securely powering products from the sensor to the smartphone to the supercomputer. This technology combined with our IoT software and end-to-end connectivity, device and data management platform enable customers to derive real business value from their connected devices and data. Together with our 1,000+ technology partners we are at the forefront of designing, securing and managing all areas of compute from the chip to the cloud.

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