Low-voltage serial quad I/O memory device leans on SuperFlash technology to cut power, latency

September 4, 2017 Brandon Lewis

Microchip has released the SST26WF064C, 1.8 V serial quad I/O SuperFlash memory device. The SST26WF064C is a 64 Mb device that combines Dual-Transfer Rate (DTR) technology with SuperFlash NOR Flash memory, allowing designers of wireless and battery-powered applications to reduce overall power consumption.

DTR provides the ability to output data on both edges of the clock for faster data access, while SuperFlash provides erase times between 35 and 50 milliseconds. SuperFlash technology is built on a split-gate Flash memory cell, which enables high-endurance cycling of up to 100,000 write/erase cycles and data retention of more than 100 years.

Both technologies help limit power consumption by performing operations more quickly.

“Microchip continues to invest in and introduce memory products based on SuperFlash technology,” said Randy Drwinga, vice president of Microchip’s Memory Products business unit. “The SST26WF064C is our highest-density low-voltage device to date and, along with other products, we will continue to offer them for the long product life cycles of our automotive, industrial, and medical customers.”

The SST26WF064C operates at frequencies of up to 104 MHz, providing low-latency execute-in-place (XIP) functionality without the need for SRAM code shadowing. The device leverages a 4-bit multiplexed I/O serial interface, and utilizes a SPI-compatible command set.

The SST26WF064C also incorporates a hardware-controlled reset functionality, which engineers can reconfigure using the HOLD# pin.

Engineers can leverage Verilog and IBIS models, as well as device drivers, when incorporating the SST26WF064C in their designs.

The SST26WF064C is available now in a variety of packaging options, including 8-contact WDFN, 8-lead SOIJ, 16-lead SOIC, and 24-ball TBGA. For more information, visit www.microchip.com/SST26WF064C.

About the Author

Brandon Lewis

Brandon Lewis, Editor-in-Chief of Embedded Computing Design, is responsible for guiding the property's content strategy, editorial direction, and engineering community engagement, which includes IoT Design, Automotive Embedded Systems, the Power Page, Industrial AI & Machine Learning, and other publications. As an experienced technical journalist, editor, and reporter with an aptitude for identifying key technologies, products, and market trends in the embedded technology sector, he enjoys covering topics that range from development kits and tools to cyber security and technology business models. Brandon received a BA in English Literature from Arizona State University, where he graduated cum laude. He can be reached by email at brandon.lewis@opensysmedia.com.

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