Low power operation continues to be a key driver for applications in every industry. With the addition of Sleep mode, power management suddenly shifted from solely a hardware concern to something software developers had to consider.

The simplest application of power modes is that when a system is idle, you put it to Sleep. Today’s MCUs, however, offer multiple low power modes, further complicating low power design. Now developers need to consider the complex independencies of multiple cores, high-frequency signal processing, and how to reliably meet all of a system’s real-time deadlines.

I asked Greg Verge, Systems Engineer at Cypress Semiconductor, to share his experience of how to optimize use of the multiple power modes of the dual-core PSoC 6. In addition to Active (e.g. LP or Low Power) and Sleep (e.g. ULP or Ultra Low Power) modes, this Cortex M0 + Cortex M4 SoC supports Deep Sleep and Hibernate modes. Developers also have the option of lowering the core voltage to save power.

Each power mode lights up different parts of the SoC (see Table 1). Active powers the entire chip while Hibernate drives just the minimum required to maintain retention RAM, the real-time clock, and the configuration of I/O pins. The more power a mode saves, the less the SoC can do and the longer it takes to wake up back to Active mode.

Sleep mode is still your idle loop go to. The CPU clock stops but can be quickly brought back to Active mode with an interrupt or request from the other core. Peripherals can be left active and the CPU ‘immediately’ executes code from where it left off.

Deep Sleep is a lot like Sleep but with more of the chip turned off and a longer time-to-wake. The decision to use Sleep or Deep Sleep depends upon how fast the system needs to wake and which peripherals need to be active while the system is down. High-frequency clocks don’t get powered so you lose some communication links (UART) while being able to retain others (SPI and I2C). You also lose your ADCs because they require a MHz clock. Your PWMs will be gone as well, so don’t fret when LEDs go out.

Where things start to get complicated is with multiple cores. Low power modes affect both the CPU and the system. Dropping one CPU into Deep Sleep will not automatically power down system resources because the other CPU may be using them. Thus, you only get the full low power benefit if both CPUs are in Deep Sleep. If your cores are out of sync when they try to Deep Sleep, this can substantially impact your overall power efficiency.

Hibernate Mode

Hibernate mode puts the system into its lowest power state. Hibernate is a commitment since you can’t simply resume execution; the system needs to be reset. Hibernate is useful during very long sleep periods when you need just a bit of intelligence to wake the system. This can be useful for implementing power off/on functionality or operating a low-frequency sensor.

Hibernate mode also supports retention RAM to hold limited state information. For example, you could store the previous sensor reading. When you reset the system, it checks the sensor and compares the current value to the previous value. If they are within a threshold, there is no event to be triggered and the system drops back into Hibernate mode. Maximum power efficiency achieved.

Just because you’ve managed to get the CPUs into the right low power mode doesn’t mean you’re running efficiently. In Deep Sleep and Hibernate, leakage to I/O pins can dominate power consumption. Consider a pin that you’re using to bias a resistor. In addition to making sure you’re using the highest resistance you can, the pin needs to be kept high or low appropriately to minimize power drain (i.e., leakage).

Hibernate mode maintains the configuration of I/O pins so that you can keep all pins in their lowest power state. For example, it’s a common practice to tie a resistor directly to power. If you instead connect the resistor to a GPIO, rather than the resistor constantly drawing power, you can now turn the resistor on and off. If you aren’t aware of this, you might assume the system is running at a low 7 µA when a pin is actually drawing 1 ma. To put this in perspective, that’s 143X less efficient, taking a 10-year operating life down to 25 days.

Two other major factors impacting low power operation are lowering the core voltage and choice of regulator. The PSoC 6, for example, can supply its cores with 1.1 V or 0.9 V. You don’t get to clock the core as fast at 0.9V, but if you’re just checking a temperature sensor, 50 MHz is still way more processing than you need.

Choice of regulator – integrated LDO or high efficiency switch mode buck convertor – allows you to trade power efficiency for cost. Using the buck convertor gives you 90 percent efficiency, but at the cost of an external inductor.

As chip manufacturers continue to improve low power operation, our embedded systems will be able to do more with less. Just remember that with more options come more ways to undo all of your hard work optimizing a system with a single, simple misunderstanding of what the system is actually doing.

Mode Resources Available Current (Typ) Wakeup Time System Low Power - CPUs Active All with Cortex-M4 at 150 MHz 6.3 mA  - System Low Power - CPUs in Sleep All except CPU processing 0.65 mA 80 ns System Ultra Low Power - CPUs Active All with Cortex-M4 at 50 MHz 1.6 mA  - System Ultra Low Power - CPUs in Sleep All except CPU processing 0.42 mA 240 ns System Deep Sleep I2C/SPI, GPIO, WDT, RTC and Low Power Comparator wakeup sources. Programmable GPIO logic, full device state, and all SRAM. 7 uA 15 us System Hibernate GPIO, WDT, RTC and Low Power Comparator wakeup sources. Hold last GPIO state. Retention RAM. Wake only by Reset. 300 nA 500 us

Table 1: Different power operating modes enable developers to optimize run-time power consumption but you’ll still need to be careful. Shown here are the modes, current, and wakeup time for the dual-core PSoC 6 from Cypress Semiconductor.