The incredible momentum of the RISC-V ecosystem was in full force at the recent RISC-V Workshop in Barcelona, co-hosted by the Barcelona Supercomputing Center (BSC) and Universitat Politècnica de Catalunya (UPC). With over 150 organizations, individuals, academics and universities that are members of the RISC-V Foundation, it’s clear that the industry has taken notice of this new era of processor design as we see new RISC-V designs, implementations and products hitting the market regularly. We were excited to have 325 attendees with us from all over the world, making this Workshop our most successful event to date outside of Silicon Valley.
On the first day of the Workshop, industry leaders NXP and Western Digital delivered the keynote talks. The theme of the session from Robert Oshana, vice president of software engineering research and development at NXP, was how “hardware engineers are from Mars while software engineers are from Venus.” Robert’s central point was that it’s important to learn from the lessons of other open source efforts so hardware and software designers can work closer together. He discussed how open source RISC-V implementations will enable more software driven hardware designs, and talked about how NXP is innovating with RISC-V. Martin Fink, executive vice president and chief technology officer at Western Digital, talked about how big data and fast data require new architectures. Martin explained how RISC-V brings Western Digital the “freedom to innovate and create environments for data to thrive.”
Mateo Valero, director at the Barcelona Supercomputing Center, gave the keynote address on the second day of the Workshop. Mateo provided attendees with an overview of the European Processor Initiative, which is focused on designing and developing low-power RISC-V based microprocessors developed entirely in Europe. These processors will be designed with significantly better performance and energy efficiency to power exascale supercomputers, along with other applications like autonomous cars and data centers.
Throughout the event there was a drumbeat of news from member companies announcing new solutions and partnerships. Antmicro released 64-bit Linux-enabled RISC-V platform support, and announced a partnership with Thales. Esperanto Technologies partnered with NetSpeed to power SoCs for artificial intelligence, and selected UltraSoC’s embedded analytics IP for the development of massively parallel and many-core RISC-V SoCs. Express Logic announced its X-Ware IoT Platform provides support for the AndesCore N25 and NX25 RISC-V processors. SiFive and Microsemi launched the HiFive Unleashed Expansion Board; SiFive also announced Intel Capital participated in its recent Series C funding round, and unveiled its Democratizing Ideas partnership initiative.
To watch the sessions from the RISC-V Workshop in Barcelona and check out the presentations, please visit here. The RISC-V ecosystem is also seeing some big growth in APAC, so don’t miss out on upcoming events including the RISC-V Day in Shanghai taking place June 30 and the RISC-V Workshop in Chennai taking place July 18-19.
We’re thrilled with the continued growth of the RISC-V Foundation ecosystem. Together, we are unleashing a new innovation frontier with the extensible RISC-V ISA available for all to use in various micro-architectural incarnations across all forms of computing devices.