Signal- and power-integrity fundamentals are essential in a high-speed PCB

May 16, 2016 OpenSystems Media

In today’s digital design world, speed is often the main factor determining a product’s performance. Many designs are packed with too many high-speed interfaces with signal speeds high enough that the traces and layout of the printed-circuit board (PCB) play a significant role in the overall system performance.

Consequently, signal- and power-integrity issues tend to be the main causes of device failure in various product design stages. It’s prudent for design engineers to carefully consider the analog characteristics of a high speed PCB design in addition to the digital parts. Any physical phenomenon that may increase timing uncertainty of the digital waveform must be accounted for.

Signal integrity (SI) is achieved when well-defined PCB paths are implemented. These paths allow for signals to be delivered from the driver to the receiver with a clean edge at the right timing. A design with poor SI often doesn’t meet timing or jitter requirements. In some cases, a poor SI may also cause higher than acceptable radiated emissions. In the worst case scenario, the design doesn’t function at all.

Let’s discuss the key design considerations to achieve high speed SI. First is the transmission-line behavior at high frequencies. In the early days of electronics, SI wasn’t a concern due to the slow edge rate. As clock rates and signal speeds increased, the rise time consequently reduces to the point where the PCB trace lengths are on the same order of length as the edge rates passing them. For an HDMI 1.4 signal with a 2.97-Gbit/s data rate, the critical PCB length is at 2 mm. As such, transmission lines of high speed PCBs and their characteristic impedances, delays, and losses, must be carefully analyzed. These transmission-line behaviors are key to determining how the connected components interact. The most common transmission line impedance to achieve is 50 Ω.

Communications with PCB fabrication houses determine the PCB material, stack up, and identification of the trace width/clearance in each layer to meet the required impedance. Two common types of transmission lines used in PCB design are stripline and microstrip.

The stripline has the signal trace sandwiched between two reference planes. Microstrip has the signal trace routed on the outer layer and has only one reference plane. The selection between the two depends on the signal speed requirement, the design’s complexity, and the fan-out arrangement from the driver IC. In general, stripline is less susceptible to noise and microstrip offers faster signal speed path.

Once PCB material, stack up, and transmission-line type are defined, the designer needs to decide how the high-speed signals are routed. When considering the signal trace, it’s important to pick a clean and short trace with an undisrupted reference plane underneath. This lets current travel to the receiver with consistent impedance and return to the source through the path of least impedance, which is the reference plane directly adjacent to the signal trace. The common return path problems include (a) when there’s a discontinuity in the reference plane and (b) when the routed signal changes layers with no reference plane to follow underneath. The consequences of the above mentioned disrupted return paths are signal reflections and ringing.

Signal reflections and ringing are the direct results of poor signal integrity design. The driver, transmission line, and receiver impedance all could lead to signal reflections. If a signal encounters a change in the instantaneous impedance of the PCB as it propagates down, part of the signal will reflect back to its source and cause signal distortion. The change in this instantaneous impedance is called impedance discontinuity. Ringing arises when multiple reflections are present due to impedance discontinuity. If the driver, the interconnect transmission line, and the receiver are of the same impedance, there would be no reflections or ringing. Therefore, matching the same impedance between the components and interconnects is the key to reduce ringing.

Crosstalk results from signals coupling due to the PCB traces’ capacitive and inductive nature, and it can be caused by multiple signals coupled to one another from being routed too close or having signal return paths too close to one another. Crosstalk can be minimized when the routed trace and return paths are twice the trace width away from the other signal traces. Ringing also contributes to the possibility of crosstalk; less ringing translates to less crosstalk.

While not discussed here, the termination topology, the lengths of the traces, the propagation speed of the signals, and the shape of the traces all need to be considered.

Here is a summary of the practical design rules to follow to maintain SI:

  • Identify all high-speed signals during schematic design.
  • Route the highest speed signals on the top and bottom layers if possible.
  • Every high-speed connection must be treated as part of a transmission line pair, routed as 100- or 90-Ω differential pairs and 50-Ω single-ended.
  • Keep signal traces one dielectric away from the return path. Any deviation from this will increase radiated emissions, degrade signal integrity, and decrease immunity.
  • Provide good ground references at all times to the high speed signals.
  • Avoid return-path discontinuities such as voids in the reference plane.
  • If the high-speed signals transition layers and change ground reference planes, a return via must be placed next to the signal vias.
  • For differential routing, maintain positive and negative traces as balanced as possible in terms of signal and its return path and meet the intra- and inter-pair length matching requirement.
  • Maintain greater than 2x line width rule for inter-pair spacing.
  • Maintain greater than 3x line width spacing away from other interfaces.
  • No right-angle turns as they add capacitance to the trace.
  • Minimize the number of vias (layer transitions) for high-speed signal traces.
  • Minimize any stubs along the high-speed signal trace, including stubs introduced from vias.
  • Protect high-speed signals by keeping them away from noisy signals, clocks, and switching-mode power supplies.

Power integrity

Power integrity (PI) is achieved by providing a power delivery network (PDN) inside a system that complies with the required power-supply conditions of the processors and all other components. PDN is a chain of interconnects in the form of transmission planes that deliver power from a voltage regulator module (VRM) through the PCB, across the package, and through the on-die routing to the transistors themselves.

PI is harder to visualize than SI, demonstrated by the fact that there are tens and hundreds of nodes connected in the same power plane and every node affects the overall impedance in the PDN, while SI deals with only the driver and the receiver. PI problems are difficult to repeat and troubleshoot. Therefore, a complete PI study in pre- and post-layout PCB design stages are suggested. While an advanced and usually expensive PI simulation tool is required for a complete PI analysis, we’ll stick to the design fundamentals here.

A good PI system in a high-speed digital design serves two essential purposes. First, it provides stable voltage references (ground/return path) for exchanging signals. Second, it distributes power to all logic devices with acceptable noises and tolerances to keep the voltage across the chip pads constant.

It sounds simple, but a few facts need to be realized in the high-speed PCB design. First, there are typically hundreds of power and ground balls from a typical BGA processor which requires tens of power-supply voltages. Second, all of these power pins consume many amps of current. Consequently, when the device is in operation, all these power pins that consume amps of current, load all the power-supply voltages at high frequencies simultaneously.

Taking this into consideration, PI study is no longer just a purely DC analysis, but involves the studies for transient loading at high frequencies in every power rail, from the VRM to the IC pad.

Fundamental design considerations for power integrity starts with transmission plane behavior in high frequencies. Similar to SI’s transmission lines, the key in PI analysis is treating all power rails as transmission planes and analyze their characteristic impedances. To achieve good power integrity, it’s desirable for the PDN to have the lowest impedance possible. High-frequency transient noises can be generated and can propagate to the whole board if overlooked.

The main challenge is that the PDN interconnects in the PCB all have an inductive nature. Component mounting, PCB traces, capacitors, and vias, all exhibit inductance. This suggests that impedance increases as the transient frequency increases. As the VRM, capacitors, PCB stack-up, power/ground plane, and the IC all have different characteristic impedance in different frequencies, careful selection of components and placement locations are the ways to reduce transmission plane impedance.

Figures 1 and 2 demonstrate a capacitor’s inductive nature in high frequencies and the equivalent circuit for a typical PDN. Figure 1 is an example of a 0603, X7R, 1-uF capacitor’s impedance vs. frequency plot using AVX’s SpiCap simulation tool. The left half of the plot shows that the capacitance dominates the characteristic impedance between 0 and 22.5 MHz and the right half shows that the inductance dominates the characteristic impedance for frequencies greater than 22.5 MHz.

1. Example of a 0603, X7R, 1-uF capacitor’s impedance vs. frequency plot.

Figure 2 is a PDN equivalent circuit illustrating the resistive, capacitive, and inductive nature of each interconnect of the same transmission plane. All these physical phenomena require thorough study as a part of PI analysis.

2. Shown is a PDN-equivalent schematic of a typical transmission plane captured from Altera’s PDN tool.

Ideally, we want to keep the impedance throughout the transmission plane as low as possible. As many factors impact the impedance, target impedance needs to be calculated separately and independently for each voltage rail to all chips on the board. In each rail, the target impedance may vary with frequency due to the chip’s specific current requirement. The impedance and acceptable tolerance information for each rail listed in the device spec sheet should be used as starting guides when designating target impedance.

The PDN for a particular transmission plane consists of different interconnect blocks, from the VRM to the bulk decoupling capacitors to the the vias to the the traces and planes on the circuit board. Then on to additional decoupling caps, the solder balls or leads of the packages, the interconnects in the packages, and the wire bonds and the interconnects on the chips. Each interconnect block contributes to the transmission plane’s characteristic impedance. When analyzing the PDN, it’s important to study each interconnect rail first, and then the transmission plane, and then as a whole PDN system.

The Altera PDN Design Tool can illustrate how different each PDN interconnect affects the characteristic impedance of the same transmission plane in different frequency bandwidths. The tool can be downloaded with a valid Quartus II software license from Altera. Start the design process by setting the target impedance to 12.3 mΩ, and then go thru each PDN interconnect.

The low frequency impedance, ranging from DC to 10 kHz, is set by the VRM. A VRM output is typically in the order of milli-ohms from DC to 10 kHz.

3. Shown is the VRM characteristic impedance.

Practical tips to consider for a VRM PCB layout are:

  • Maximize metal thickness.
  • Use sufficiently wide power traces.
  • Use multiple parallel power and ground vias.

The bulk capacitors added in parallel to the VRM lowers the impedance by 10 to 100 kHz.

4. Shown is the bulk capacitors characteristic impedance.

Practical tips for selecting the right bulk capacitors are:

  • Follow the reference design for the bulk capacitor values.
  • Follow the design guidelines for optimal placement of bulk capacitors.

Decoupling capacitors lower the transmission plane’s impedance by 0.1 to 10 MHz. Adding decoupling capacitors close to the power pad’s entry points reduces the loop inductance. Picking the right location and selecting the right number and value of the decoupling capacitors play an important role here.

5. Shown is the decoupling capacitor characteristic impedance.

Practical tips to select the right decoupling capacitors are:

  • Engineer capacitor values, body sizes, and placement to meet impedance specification.
  • Lower power-ground loop area to reduce loop inductance.

A closely stacked power and ground improves the characteristic impedance of the PDN by 10 to 100 MHz.

6. Shown is the PCB power/ground planes characteristic impedance.

Practical tips for designing power/ground plane are:

  • The power and ground planes should be as close together as possible.
  • Place multiple vias for power and ground.

In general, for frequencies above 25 MHz, the characteristic impedance is dominated by the vias to the BGA ball, the IC package, and the on-die capacitance. To model this, a more advanced simulation tool is required.

Some other notes on decoupling caps and power/ground planes are:

  • Current always takes the path of least impedance. At these high frequencies, PDN loop inductance, value, and placement of capacitors attached to power pins dominate impedance.
  • Local decoupling capacitors should be placed as close as possible to the processor power and ground pins. When using back-side capacitors, each capacitor should have its own via directly to the ground and power plane layers.
  • Power and ground vias and planes should be as close together as possible.

Practical design rules for PI are:

  • Use power and ground planes on adjacent layers, with as thin a dielectric as possible.
  • Use surface traces as short and wide as possible between the decoupling capacitor pads and the vias to the buried power/ground plane.
  • Place the capacitors where they’ll have the lowest loop inductance.
  • Use SPICE models to help select the optimum number of capacitors and their values to bring the impedance profile below the target impedance.
  • Local decoupling capacitors must be placed as close to the processor pins as possible.
  • Orient capacitors to minimize loop inductance.
  • Place local vias in the return path.

With higher clock rates and signal speeds in every digital design, attention to SI and PI is crucial to designing a well performing product. Although I explained SI and PI as separate topics, they are closely related and their issues can influence each other. Furthermore, a high-speed PCB with careful SI and PI design considerations usually has minimal electro-magnetic interference issues.

Chris Yao is currently a senior hardware design engineer at Intrinsyc Technologies, where he works with software engineers and customers to define and develop cutting edge electronic products. Since joined Intrinsyc in 2014, he has been working on Qualcomm’s Snapdragon solutions in various projects. As a team member of the hardware group, he specializes in high speed digital design.

Chris Yao, Senior Hardware Design Engineer, Intrinsyc Technologies
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