With a goal of providing better support for embedded Linux and other high-end operating systems, the DesignWare ARC HS38 processor IP core delivers up to 4200 DMIPS at speeds up to 2.2 GHz in typical 28 nm silicon. Designed by Synopsys, the core’s performance and low power consumption suit it for the growing embedded control and signal processing demands of devices such as home routers and gateways, data centers, digital TVs, networked appliances, and automotive infotainment.
The ARC HS Processor Family runs the ARCv2 instruction-set architecture (ISA), which enables the implementation of high-performance embedded designs with low power consumption and a small silicon footprint.
The HS38 has a full-featured memory management unit (MMU) supporting a 40-bit physical address space and page sizes up to 16 MB. Multicore configurations (dual- and quad-core) are available with support for SMP Linux, full Level 1 (L1) cache coherency, and up to 8 MB of L2 cache. An optional floating-point unit accelerates computations with support for single- and double-precision arithmetic instructions.
The processor is supported by the Synopsys MetaWare Development Toolkit, which is useful for developing, debugging, and optimizing embedded software on ARC processors. The kit includes an optimized C/C++ compiler, a debugger for maximum visibility into the software, and a fast instruction set simulator for pre-hardware software development.