Power supply sequencing for an FPGA
December 22, 2014
Power supply sequencing is an important aspect to consider when designing a field programmable gate array (FPGA) power design. Typically FPGA vendors...
Power supply sequencing is an important aspect to consider when designing a field programmable gate array (FPGA) power design. Typically FPGA vendors specify power sequencing requirements, as there can be anywhere from three to more than ten rails powering an FPGA.
By following the recommended power sequence, excess current being drawn during startup can be avoided, which in turn prevents damage to your device. Sequencing the power supplies in your system can be accomplished in several ways. This article elaborates on different sequencing solutions that can be implemented based on the level of sophistication needed by your system.
Sequencing solutions
Sequencing solutions include:
1. Cascading PGOOD pin into enable pin
2. Sequencing using a reset IC
3. Analog up/down sequencers
4. Digital system health monitors with PMBus interface
1. Cascading PGOOD pin into enable pin
A basic, cost-effective way to implement sequencing is to cascade the power good (PG) pin of one power supply into the enable (EN) pin of the next sequential supply (Figure 1). The second supply begins to turn on when the PG threshold is met, usually when the supply is at 90 percent of its final value. This method offers a low-cost approach, but you cannot control the power-down sequence or adjust timing. Adding a capacitor to the EN pin gives you some flexibility to introduce timing delays between stages. However, this method is unreliable during temperature variations and repeated power cycling, and it still cannot support power-down sequencing.
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2. Sequencing using a reset IC
Another simple option to consider for power-up sequencing are reset ICs with time delay. With this option, the reset IC monitors the power rails with tight threshold limits. Once the power rail is within three percent or less of its final value, the reset IC enters the wait period defined by the solution before powering up the next rail. The wait period can be programmed into the reset IC using EEPROM or be set by external capacitors. You can use a multi-channel reset IC to power up the different rails for FPGA solutions (Figure 2). The advantage of using reset IC for power-up sequencing is that the solution is monitored, which helps confirm that the previous rail is within regulation before releasing the next rail without the need of a PGOOD pin on the power converter. The drawback of using a reset IC solution for sequencing is that it does not implement power-down sequencing.
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3. Analog up/down sequencers
Implementing power-up sequencing can be easier than implementing power-down sequencing. To achieve power-up and power-down sequencing, there are simple analog sequencers (Figure 3) that can reverse or even mix the power-down sequence relative to the power-up sequence. Upon power up, all the flags are held low until EN is pulled high. After EN is asserted, each flag goes open drain (pull-up resistor is required) sequentially after an internal timer has elapsed. The power-down sequence is the same as power up, but in reverse order.
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Cascading multiple sequencers
Sequencers can be cascaded together to support as many power rails as your system holds, as well as provide fixed and adjustable delay times between enable signals. In Figure 4 two sequencers cascade together to achieve six sequenced rails. Upon power up, the AND gate ensures that the second sequencer does not trigger until it has received both an EN signal and rail C has triggered. On power down, the AND gate ensures that the second sequencer sees EN falling edge, irrespective of output C. The OR gate ensures the first sequencer is turned up when EN rising edge triggers. Upon power down it makes sure the first sequencer can’t see EN falling edge until D has fallen. This guarantees power-up and power-down sequencing, but does not offer a monitored sequence.
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Monitored up/down sequencing
Monitored sequencing can be achieved by simply adding a couple of AND gates between the FlagX output and the PG pin of the previous supply (Figure 5). In the example shown, PS2 is enabled only if PS1 is greater than 90 percent of its final value. This method offers a low-cost, monitored sequencing solution.
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4. Digital system health monitors with PMBus interface
If your system requires the utmost flexibility, use a PMBus-compatible digital system health monitor. These offer maximum control for any sequencing needs by allowing the user to configure ramp up/down times, on/off delays, sequence dependencies, and even voltage and current monitoring.
Digital system health monitors come with a graphical user interface (GUI) that can be used to program power-up and power-down sequencing along with other system parameters (Figure 6). Some digital system health monitors also have non-volatile error and peak-value logging that helps with system failure analysis in case of a brownout event.
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FPGA sequencing requirements examples
FPGA vendors such as Xilinx or Altera give either a recommended or required power-up sequence within their datasheets that are easily accessible online. Sequencing requirements vary between vendors and vary from one vendor’s FPGA family to another. Also listed in their datasheets are timing requirements for ramp up and shutdown. The recommended power down sequence is typically the reverse order of the power up sequence. An example of power up sequencing is shown in Figure 7.
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