Cadence Design Systems launched the latest IP in the Tesilica Fusion family, the G3. The DSP serves as a fixed and floating-point VLIW processor designed for multi-purpose, compute-intensive signal processing applications. General-licensing availability begins this October.
The high-performance DSP gives designers and developers flexibility in their hardware and software choices. It’s also designed to enable easy implementation, offering an auto vectorizing compiler and an extensive kernel library. Hence, programmers can port hardware in C/C++.
The G3, based on Cadence’s 32-bit Xtensa LX7 control processor, is the newest addition to the Fusion family, joining its only relative, the F1. By catering to applications that require higher performance, the G3 offers some juxtaposition to the F1 offering.
Like its predecessor, the G3 boasts scalability thanks to its extensive DSP ISA. But while the F1 caters to more resource-constrained designs like wearables, the G3 is intended for more demanding applications like audio processing, imaging, and baseband signal processing. The DSP is enabled with quad 32-bit integer MACs and quad single-precision 32-bit floating-point MACs.
Here are some additional highlights:
- 128-bit 4-slot VLIW DSP architecture
- 128-bit SIMD architecture, supporting 4-way (32-bit)
- Fixed-point (32-bit) MACs
- Floating-point single precision (32-bit) FMAs or MACs
- Optional memory protection unit (MPU)
- Optional integrated DMA controller
- Scatter/gather/histogram supported operations capable of low-end image processing and pattern recognition