The technological trend in Microcontrollers (MCUs) and related devices is smaller geometry, and with that the need for much smaller operating voltages. Circuit designers are challenged to connect low-voltage signals to the wide variety of other device voltages. The I2C Bus poses a unique problem to these efforts with its defined protocol and bidirectional signal flow. Integrating a level-translating bus buffer Application Specific Standard Product (ASSP) can address this issue, but comes with its own set of obstacles.
The latest embedded computing devices have lower supply voltages due to advancing technology in semiconductor fabrication. This is creating smaller transistor geometries, which in turn means lower breakdown voltages. As a result, signal swings are now much smaller than before, to as low as 1 V (Figure 1).
For a pure digital signal there are several interface devices available that can translate the smaller signals to higher swings for CPU output ports. Similarly, these same devices can be used to step down existing signals to smaller and safer inputs for a new low-voltage core. For instance, Voltage-Level Translators (VLTs) address any mismatch of signal operating voltages, but bidirectional VLTs are tricky to design. Application Specific Standard Products (ASSPs) address the problem.
I2C bus basics
The I2C bus relies on two electrical connections and two external resistors for full bidirectional signaling. The protocol is comprehensive, allowing multiple nodes to act as both transmitter and receiver while avoiding bus collisions thanks to a simple and reliable multi-master arbitration.
The flow of data on the I2C bus is controlled by the master, which supplies a clock signal called the Serial Clock (SCL). Data is passed along a second electrical connection, called Serial Data (SDA), and data on SDA may flow from the master to the slave, or in the other direction.
A unique feature of the I2C bus is the Wired-OR logic connection of nodes. When the bus is idle, none of the nodes draw current and the bus signals are held at logic 1 (typically +5 V) by the pull-up resistors, one each on the SCL and SDA. Signals are asserted by a node pulling these lines low through an open-drain driver (though older devices built on bipolar technology use an open collector device for the same outcome). The master initiates each data transaction, and the responding node pulls the SDA line low (the responding device may also pull the SCL line low, but this mode, called "clock stretching," is rarely used).
Bidirectional Voltage Level Translators (VLTs)
There is no hardware flow control in the I2C bus protocol, which makes VLTs protocol agnostic but also creates a circuit design challenge (Figure 2).
Data flow direction changes on the I2C bus often occur frequently, in fact after each eight clock cycles or the delivery of one byte of data. The ninth clock period reads the slave device to confirm the sent data has been understood. During the ninth clock period the master looks on the SDA line for either a logic 0 acknowledge (called "ACK") or a logic 1 not acknowledge (called "NACK"). It falls to the VLT to pass these signals back and forth reliably.
In the first generation of VLT designs, the typical voltage step was from 5 V on the high side to 3.3 V on the low side (usually the side with new technology). A common and low-cost translation solution was the single Field-Effect Transistor (FET) device (Figure 3).
Limitations creep into this topology. While the single FET can pass signals in both directions, with appropriate VLTs there's no isolation. Loading on one side has to be carried by the other side, putting a limit on their appeal. Worse yet, the available low-cost FETs are not well suited to these lower bus voltages. Imagine the case of a 1 V to 2.5 V interface required for connecting a CPU core (1 V signals) to the controller seen in a DDR4 RDIMM design (a 2.5 V part). FETs with lower gate thresholds are necessary and available – for a price – but I2C bus buffer ASSPs can also address these lower bus voltage designs. A superior solution to FET-based VLTs is the I2C bus buffer ASSP.
I2C bus buffer Application Specific Standard Products (ASSPs)
ASSPs to support I2C expansion have been around for a while, and newer designs address VLT over an impressive range, including the next generation of CPUs and Systems-on-Chip (SoCs) that run on only 1 V supplies. Because ASSP devices are buffers, they separate loading to each side of the I2C bus buffer. This is important for not burdening the CPU or the SoC's I/O pins, and allows for the attachment of even more nodes on the other side of the buffer device; for example, new smart phone and personal electronic architectures have many more sensors (nodes) that are attached to the I2C bus.
Caution is needed when adding any bus buffer to a design because these devices must manipulate the bus voltage levels to avoid a deadly bus lockup condition. Simply put, an I2C bus buffer must determine if a low on side "A" is from its own output (that is, the buffered low coming in on side "B") or another external device on the side "A" bus.
Bus buffer designs use one of a handful of techniques that change the bus buffer's output voltage. In one such method, a small offset voltage is added that is small enough to not interfere with other devices on the bus but big enough for the bus buffer to know the difference between an external (and much lower) signal from another node on the bus, as well as its own logic 0 signal. A typical static offset is only 90 mV.
Bus speed improvements
While early I2C buses moved at modest speeds (clocking in at 100 kHz or less) and served the applications of the day, newer applications demand more data throughput and therefore faster clocks. The current I2C specification, which defines the timing of signals, has added several new clock speeds up to 1 MHz. Called "Fm+" (Fast mode plus), these clock speeds are 250 percent faster than the previous Fm (Fast-mode) speed increase that limited clocks to 400 kHz.
Keep in mind that it is the action of the bus master – often a function already built into the MCU, CPU, or SoC device – that determines the bus clock speed. Slave devices and bus buffers don't generate clocks, and don't care about clock accuracy; an 800 kHz bus clock might actually operate with a 20 percent tolerance. To increase speed the bus loading (capacitance) must be reduced. Bus buffers split the bus and isolate capacitance for each segment.
Increasing the clock frequency is not without its hardware challenges. Untamed faster clock and data transitions will likely cause ringing and undershoot, because the I2C bus is not a transmission line and does not have adequately small termination resistors to dampen fast signal edges. The I2C specification puts limits on both the rise time and fall time of edges. Rise times of the bus segments are set by the system loading capacitance, which is the sum of node and interconnecting signal trace capacitances. Board-level circuit designers only have freedom to select the I2C bus signal pull-up resistors.
When the I2C bus is driven by modern high-performance digital devices (CPU, MCU, and SoC types), care is needed to slow down the falling edge of both the clock and data bus signals generated by these lightning-fast devices. If necessary, an external series resistor should be added to work with the stray capacitance to create a controlled fall time and dampen any ringing on the I2C bus segment. Alternatively this can be achieved by adding a small capacitor.
If a design needs more data throughput and newer technology components that operate from lower supply voltages, expect to add an I2C bus buffer to your design (Figure 4). Treat the two sides of the I2C bus buffer as separate buses, and choose pull-up resistors to suit.