Virtual platform for RISC-V: Zero to Linux in 5 seconds or less
March 15, 2018
Product
Imperas has developed and released open source models of all the common instruction set extensions of the RISC-V ISA.
Imperas Software, Ltd. formed part of the growing ecosystem of support for RISC-V, together with six other members, at the RISC-V Foundation booth at embedded world in Nuremberg, February- March 2018. Imperas featured a demo of the RISC-V virtual platform, showcasing both FreeRTOS and Linux booting.
The RISC-V foundation sponsored a daily prize drawing for two of the latest RISC-V hardware development boards. For attendees who didn't win, or anyone not able to attend the show, there is good news: Imperas has developed and released open source models of all the common instruction set extensions of the RISC-V ISA including RV32E, RV32IMAFD, RV32GC, RV64IMAFD, RV64GC through the Open Virtual Platforms (OVP) website. These RISC-V models, together with other OVP models, APIs and the OVPsim virtual platform simulator, enable the building and customization of instruction accurate models and platforms for custom SoC subsystems, full SoCs, or larger systems for software development.
The Imperas team presented two technical papers at the conference:
The first, Virtual Platform Environment for the Bring Up and Test of a Secure Many-Core AUTOSAR RTOS (Real Time Operating System), by Atsushi Shinbo and Shuzo Tanaka of eSOL TRINITY Co., Ltd., Masaki Gondo, eSOL Co., Ltd., Duncan Graham and Larry Lapides, Imperas Software Ltd., discusses a virtual platform environment for the bring up and test of a secure many-core RTOS for automotive use. It presents the RTOS challenge on automotive system and covers virtual platforms for software development, the building of virtual platforms, information on eMCOS RTOS and AUTOSAR, and discusses how to debug and test an RTOS.
The second, Using an Instruction-accurate Simulator with Timing Estimation to Provide High-performance Cycle-approximate Simulation Results for RISC-V Processors, by Lee Moore, Duncan Graham and Simon Davidmann from Imperas Software Ltd., and Felipe Rosa from Universidad Federal Rio Grande Sul Brazil presents an approach to cycle-approximate simulation of RISC-V processors using instruction-accurate simulators. It explains why timing estimation is important for the design of embedded systems and the current techniques used. Instruction-accurate simulation is introduced and then the paper explains the approach of adding timing estimation to provide fast cycle approximate simulation. Results are presented for Andes, SiFive, and Microsemi RISC-V cores.
Imperas partners Andes, Ashling, Microsemi, and the prpl Foundation also participated, as well as other members of the RISC-V Foundation.
