System-on-Chip designs aren’t getting smaller, so the verification strategy has to get faster to deal with complexity and obtain solid results in an acceptable amount of time. Emulation presents one verification method that can do this.
Such multilevel debugging methodology would not be possible with software simulators because they are too slow to effectively execute embedded software. Likewise, the same methodology would not be possible with FPGA[
]-based prototypes since they lack visibility and access into the design to trace hardware bugs.
New emulation platforms
Increasing time-to-market pressures, along with escalating hardware/software integration and quality concerns imposed on engineering teams, make the verification process a strategically important step in chip design. A new generation of cost-effective emulators such as EVE’s ZeBu-Server (for Zero Bugs) capable of handling up to 1 billion or more ASIC gates at high speeds reaching several megahertz provides a great choice for large designs.
Lauro Rizzatti is general manager of EVE-USA. He has more than 30 years of experience in EDA[] and ATE, and has held responsibilities in top management, product marketing, technical marketing, and engineering.
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