Industry dynamics are driving seemingly insatiable demand for higher bandwidth and higher system-level performance while facing more stringent mandatory requirements to reduce power consumption. At the same time, competitive pressures are forcing customers to increase productivity without sacrificing innovation and differentiation. To meet these demands, Xilinx(r) 7 series FPGAs leverage the unprecedented power, performance, and capacity enabled by TSMC’s 28 nm high-k metal gate (HKMG), high performance, low power (HPL) process technology and the unparalleled scalability afforded by the FPGA[] industry’s first unified silicon architecture to provide a comprehensive platform base for next-generation systems.

The rapid change in today’s design environment requires a programmable solution that provides the highest performance and lowest power at the lowest cost. To meet the needs of high-volume systems, it is essential that the solution uses the latest 45 nm high-volume technology.

Xilinx delivers the first automated, fine-grain clock-gating solution that can reduce dynamic power by up to 30% in Virtex(r)-6, Spartan(r)-6, Kintex(tm)-7, and Virtex-7 FPGA[] designs. Xilinx intelligent clock-gating optimizations are automatically performed on the entire design, introduce no new tools or steps to the flow, and generate no changes to the existing logic or to the clocks that alter the behavior of the design. And, in most cases, the timing is also preserved.

This white paper describes several aspects of power related to the Xilinx(r) 28 nm 7 series FPGAs, including the TSMC 28 nm high-k metal gate (HKMG), high performance, low power (28 nm HPL or 28 HPL) process choice. The power benefits afforded by the 28 HPL process and its usefulness across Xilinx’s full product offerings is described as well as the architectural innovations and features for power reduction across the dimensions of static power, dynamic power, and I/O power.

Texas Instruments is world’s first semiconductor company to license EtherCAT technology and integrate it into the Sitara AM335x ARM generation of ARM Cortex-A8-based microprocessors (MPUs). This whitepaper explores implementation of this technology on the AM335x processor through its programmable real-time unit (PRU)-based programmable technology to create a unified front-end for industrial communications and bring EtherCAT and other industrial standards to its growing platform of ARM-based microprocessors.

RTL simulation is no longer capable of providing all of the verification required for today’s complex designs. Modern systems are a complex mixture of hardware and software, digital and analog[], and the boundaries of the system are often difficult to define.

The focus on safety-critical applications in both the automotive and industrial markets is significantly growing, bringing new and added pressures to systems engineers as they work to solve safety challenges.

Developers, learn how to create secure code. This course will teach you the essential secure coding principals for C/C++, along with the technical details of buffer overflows, and much more.