SecureRF and Intel deliver future-proof FPGA security

September 28, 2017 ECD Staff

SecureRF and Intel have collaborated to provide engineers with quantum-resistant authentication and data protection solutions for Intel FPGA-based IoT projects. The first security toolkit, available now, addresses Intel's DE10-Nano development board, a platform aimed at developers who require design flexibility, performance, and expanded I/O options when creating their IoT applications. To ease implementation, SecureRF is providing a complete SDK and has authored an article on authenticating remote devices with a Cyclone V System-on-Chip (SoC) FPGA.

Intel FPGA-SoC devices are suited for a host of functions, including acting as an IoT gateway that can authenticate and control hundreds of remote endpoints. Low-resource endpoints, often running on 8- or 16-bit processors, limit the options for strong security that must also run on an IoT gateway.  Legacy security methods such as ECC can be computationally too expensive. SecureRF’s security toolkit includes the Ironwood Key Agreement Protocol (Ironwood KAP) and the Walnut Digital Signature Algorithm (WalnutDSA), which are designed to run on the smallest processors. Based on Group Theoretic Cryptography methods, SecureRF’s solutions are up to 60 times more efficient than ECC, consume up to 140 times less energy, and are quantum-resistant to all known attacks.

Developers can download an SD card image of SecureRF’s security tools from its Security Toolkit webpage. The image includes WalnutDSA and Ironwood, as well as three separate demonstrations showing the operation of the signature algorithm and the key agreement protocol. Ironwood enables two endpoints to generate a shared secret over an open channel, while WalnutDSA lets one device generate a document that can be verified by another device. Both methods are implemented partially in software on the Intel Cyclone V’s ARM Cortex-A9 and partially in the FPGA’s fabric. All the compute-intensive routines are executed in hardware, for better performance.

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