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 4DSP's serial front panel data port core for FPGA is based on the ANSI/VITA 17.1-2003 standard - This intellectual property core can be implemented on any Xilinx FPGA families
- Up to 2.5 Gbps (using MGTs)
- Up to 230 MBps per optical transceiver
- Unidirectional and bi-directional links
- Framing supported: dataflow control; PIO per specification; copy mode; copy-loop mode; and CRC
- Fully compliant ANSI/VITA 17.1-2003 SFPDP standard
- Target devices: Xilinx Virtex-4; Virtex-5
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Product Entered: 2009-10-22,
Last Modified: 2009-11-04 |
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