Mentor and Ixia recently announced an integration that bridges the gap between pre-silicon verification and post-silicon validation. Ixia’s IxVerify virtual test tool for pre-silicon testing – working in collaboration with the– aims to catch logic errors and thus identify and resolve defects during the system on chip (SoC) verification flow.
It’s worth noting the difference between verification and validation in this context. Verification ensures that a chip design matches the functional specification at the block, subsystem, or system level. On the other hand, validation ensures that the design meets the device requirements and functions correctly in the field. And here is where emulation-based flows address both the pre-silicon verification and post-silicon validation domains.
Hardware emulation engines, primarily used for pre-silicon validation, are now seen as the hub in the verification cycle for SoC design. Why?
- First, verification of intellectual property (IP) and subsystem blocks is necessary early in the development cycle of modern, complex SoC designs.
- Second, time-to-market windows are shrinking in many markets, and the faster a semiconductor vendor can bring the chip to market, the better.
- Third, the large chipsets in networking and graphics applications come with a significant amount of software – stacks, middleware, boot code, drivers, etc. – and it’s becoming imperative that these software components are tested way ahead of silicon availability.
So, software development teams are now working closely with pre-silicon testing teams to validate both hardware and software earlier in the verification flow. Here, in big chips with a lot of computation, hardware emulation stands out with its ability to debug large data sets and embedded software, which requires exhaustive testing amidst billions of verification cycles.
From ICE to virtual emulator
Moreover, emulation technology now offers software teams a familiar debug environment. However, the traditional in-circuit emulation (ICE) approach falls short in large SoC designs with many ports. That’s because the ICE environment requires external hardware in the form of speed adapters to interface with the chip. This configuration is raising concerns in terms of port scalability, reliability, and cost.
Not surprisingly, therefore, modern SoC designs that demand billions of verification cycles are moving from the ICE mode to an acceleration mode and then to virtualization mode. That lets engineers test chips during the pre-silicon stage using a virtual emulation environment, which is made possible by transaction-based communications between the emulator and the testbench running on the workstation; part of the hardware peripherals is modeled in the emulator, and another part is modeled as an application in the workstation.
Mentor took the lead in the move to virtualization withfor pre-silicon testing of large SoC designs for networking, datacenter, and graphics applications. Veloce VirtuaLAB provides software-based verification while eliminating the need for external hardware as required in the ICE setup. It moves emulation from lab setting to the datacenter environment so that multiple design teams can have access from global locations. Think of it as a “Virtual ICE” concept.
Software imperatives and time-to-market pressures are moving the emulation value proposition left in the SoC design cycle toward the pre-silicon testing realm. And here, virtual emulation tools like Veloce VirtuaLAB that link the emulator to workstation-based software debug tools can play a crucial role in processing huge amounts of data and finding bugs way before silicon is ready for production.