AMD ups the processor core ante by 40%

August 29, 2016 OpenSystems Media

AMD recently released the details of its latest X86-based microprocessor core, dubbed Zen. Designed from scratch (mostly), the core achieves about a 40% improvement in instructions per clock, which is a pretty big deal if it pans out. Power improvements come from the ability to turn off power in parts of the chip that aren’t being used.

According to the core’s architects, the specific design improvements include a new cache hierarchy, improved branch prediction, and simultaneous multithreading. The result of these improvements are faster data fetching, better predictions of what kind of data is being employed, and the processing of more simultaneous instructions. AMD claims that these advances allow the parts to operate in fanless systems, which is not typical for such high-end CPUs.

One way Zen will be implemented is in an eight-core, 16-thread desktop processor, called Summit Ridge. According to AMD, the part will outperform a similarly configured eight-core, 16-thread Intel Broadwell-E processor when running the multi-threaded Blender rendering software with both CPUs set to the same clock speed.

There will also be a 32-core, 64-thread Zen-based server processor, codenamed Naples. In a dual-processor server, this part runs the Windows Server operating system. The Zen core features multiple architectural advances designed to increase performance, throughput, and efficiency when deployed in these upcoming microprocessors.

The Summit Ridge part employs the AMD AM4 socket, one that’s compatible with seventh-generation AMD A-Series desktop processors (previously codenamed Bristol Ridge), providing scalability for the entire line of products. AMD says that the first desktop systems featuring these A-Series processors and AM4 sockets will ship in the second half of this year.

Other features of the AM4 platform include DDR4 memory, dedicated PCIe Gen 3 lanes (so no stealing from other devices), 10-Gbit/s USB 3.1 Gen2, NVMe, and SATA Express.

Rich Nass, Embedded Computing Brand Director
Previous Article
Latest DSP IP suits high-end applications
Latest DSP IP suits high-end applications

Cadence Design Systems launched the latest IP in the Tesilica Fusion family, the G3. The DSP serves as a fi...

Next Article
Now on the Development Kit Selector: Teensy 3.2

Last week our Technology Editor, Brandon Lewis, announced the reboot of our development kit selector. Every...

×

Stay updated on processing and related topics with the Processing edition of our Embedded Daily newsletter

Subscribed! Look for 1st copy soon.
Error - something went wrong!