Santa Clara, CA. Microchip Technology Inc., via Microsemi Corporation, its subsidiary, announced it will expand its Mi-V ecosystem by revealing the architecture for a new class of SoC FPGAs. It will combine the PolarFire FPGA family with a complete MPU subsystem based on the open, royalty-free RISC-V instruction set architecture (ISA).
The new PolarFire SoC architecture provides real-time deterministic asymmetric multiprocessing (AMP) means to Linux platforms in a multi-core coherent CPU collection. SiFive collaborated in the development of the PolarFire SoC architecture that has a flexible 2 MB L2 memory subsystem with potential configuration as a cache, scratchpad or a direct access memory. Designers now have the option to implement deterministic real-time embedded applications along with a highly-functioning operating system for a myriad of thermal and space hindered applications in collaborative, networked IoT systems.
The PolarFire SoC architecture includes:
- extensive debug capabilities
- 50 breakpoints
- passive run-time configurable Advanced eXtensible Interface (AXI) bus monitors and FPGA fabric monitors
- Microchip’s built-in two-channel logic analyzer SmartDebug
- single error correction and double error detection (SEC-DED) on all memories
- physical memory protection
- a differential power analysis (DPA) safe crypto core
- defense-grade secure boot and 128Kb flash boot memory
“As a fully customizable, programmable RISC-V platform, the PolarFire SoC architecture gives designers the freedom to create innovative Linux-based SoCs in novel and interesting ways tailored for their distinct, domain-specific requirements,” said SiFive CEO Naveed Sherwami. “By leveraging SiFive’s market-leading U54-MC CPU core complex, PolarFire SoC will enable designers to overcome the universal challenge of building real-time systems with predictable behaviors.”
For more information, visit www.microchip.com.