Andes, INVECAS Partner on Advanced-process RISC-V SoCs

December 1, 2018 Brandon Lewis

SAN JOSE. Andes Technology and INVECAS are partnering to design SoCs based on RISC-V IP on advanced fab process technology, including 7nm, 14nm, 16nm, 22nm FDX, and 28nm HPC. The collaboration will pair INVECAS’ front- and back-end SoC design expertise with Andes’ RISC-V IP offerings, including the A25/AX25, N25/N25F, and NX25/NX25F 32- and 64-bit CPU IP cores.

“INVECAS will leverage its design expertise with Andes’ new RISC-V IP Cores to provide a fast-track for SoC design teams wanting to implement the open-source RISC-V IP core without the delay of coming up to speed on this new open-source CPU instruction set architecture,” says Taher Madraswala, EVP and GM of INVECAS. “INVECAS has already implemented the Andes CPU IP cores for control on test shuttles in the most advanced process nodes. We also look forward to development of platforms for vertical markets in the near future.”

The ultimate goal of the partnership is to extend 64-bit RISC-V technology into applications such as AI and deep learning, as well as market segments like IoT, automotive, bio-medical, and hand-held devices.

 

About the Author

Brandon Lewis

Brandon Lewis, Editor-in-Chief of Embedded Computing Design, is responsible for guiding the property's content strategy, editorial direction, and engineering community engagement, which includes IoT Design, Automotive Embedded Systems, the Power Page, Industrial AI & Machine Learning, and other publications. As an experienced technical journalist, editor, and reporter with an aptitude for identifying key technologies, products, and market trends in the embedded technology sector, he enjoys covering topics that range from development kits and tools to cyber security and technology business models. Brandon received a BA in English Literature from Arizona State University, where he graduated cum laude. He can be reached by email at brandon.lewis@opensysmedia.com.

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