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IP-Embedded Systems Conference Program (Dec. 1-3, 2009) Grenoble - France
5 weeks 1 day ago

Don't miss the opportunity to attend the unique three days event

IP-Embedded Systems Conference

Hold in Grenoble on December 1-3 and covering all you need to know from IP to SoC to Embedded Systems.

A tentative exciting program is now available.

View it at a glance or click on specific items you may be interested in.

Keynote Talks

- "The 21st Century Business Model Adventure" by Eric Schorn, Vice President of Marketing, Processor Division, ARM Ltd

- "Strategies for Managing SoC IP Risks at Advanced Process Nodes" by Yervant Zorian, Vice President & Chief Scientist, Virage Logic

- "Prototyping Using IP at Multiple Abstraction Levels Enables Embedded Software Development" by Joachim Kunkel, Vice President and General Manager, Solutions Group, Synopsys

- "Building High-performance lower power media-intensive consumer products isn't easy!" by Michael Dimelow, Director of Marketing, Processor Division, ARM

- "Embedded Software - Technologies and Trends" by Bernard Candaele, Deputy Director Embedded Systems TBU, Thales

- "Challenges and Opportunities for Multiple OS Architecture" by Emmanuel Petit, Head of the Systems Team, Mentor Graphics

Panels

- IP Reuse vs. IP Leverage: What's the difference, and what are the issues?

- Design and Reuse -The impossible dream?

- Total IP Solutions for Enabling Technology Adoption

- Improving IP Quality vs. Losing Design Productivity - What Are the Tradeoffs?

- How to do volume scalable chip designs in a cost conscious environment

- Transactors: where the virtual world meets the implementation world

- The evolution of semiconductor business models: is the fabless dead or alive and kicking?

- Debug and optimisation of embedded software & SoC designs: can scalable on-chip system visibility be delivered cost-effectively?

- System Level IP: Challenges and Issues

- From Processors to FPGAs to SoCs ? what are the best solutions to program algorithms onto hardware?

- R&D in Europe teams up to master future system design

Visionary scientific seminars

- Future in IP interconnects: optical, 3-D, Wireless, what are the main challenges?

- Next massively Parallel computing

- TLM Verification for Systems-on-Chip

- Computational Models for Embedded Software

- IP Management for internal and External IPs

Technical sessions

- IP Business Model & Standardization

- Design (1)

- Design (2)

- Prototyping

- IP Quality & Validation

- Performance Evaluation

- Analog Design

- Design Methodology

- Multiprocessing

- Verification

- System Debugging

- System Modelling

- Embedded Software

- Embedded Systems

- Embedded Systems Design & Debug

- Forum on Design

- Forum on Evaluation & Verification

Exhibition

In addition to the IP & ESC 09 working conference, the attached exhibition gives you the opportunity to see the reality of an Embedded System connected world.

The exhibition will allow you to meet the most advanced suppliers and see the latest products.

The foils of previous years' "IP Based SoC Design" events presentations are available online:

IP'08 Archive

IP'07 Archive

IP'06 Archive

IP'05 Archive

IP'04 Archive

IP'03 Archive

IP'02 Archive

IP'01 Archive

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Design And Reuse S.a.

International:

+33 476 21 31 02

Contact US

World Headquarters:

Design And Reuse S.A.

12 rue Ampere

Bp 267

38 016 Grenoble Cedex 1

France



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