Unique Challenges in Verifying Automotive SoCs

November 14, 2017 T&VS

Automotive is poised to be the next major growth engine for the semiconductor industry. The future envisioned for road transport is on-demand electric vehicles that are fully autonomous and semiconductors will have a huge role to play in achieving that vision.

Verifying & Validating the chips designed for automotive applications like ADAS, V2X, Infotainment and Autonomous Driving present unique challenges from a safety and security perspective.

T&VS is glad to play its part in demystifying some of these challenges by hosting a DVClub Conference on this topic on the 24th November at Bangalore. Verification & Validation enthusiasts are welcome to partake the insights that automotive V&V experts will be presenting on this subject.

 

Event Summary

 

Theme: Unique Challenges in Verifying Automotive SoCs

 

Date: 24th November 2017 (Friday), 9:30 AM – 12:30 PM (IST)

Mode: In-Person & Webinar

Venue Details: Cadence Design Systems – RMZ Eco World Road, Bengaluru, KA 560037, India – View Map

 

Agenda

 

Welcome and Introduction

Are we Ready for New set of Verification challenges posed by Automotive SoC’s

 

Lokesh Babu Pundreeka, Director, System Verification Group, Cadence

Autonomous driving is becoming real and it is demanding more safe and secure Electronic components (IC’s) for making autonomous vehicle are safety and reliable. Experience and learning from consumer and mobile ASIC’s design and verification may not enough to meet requirements for Automotive SoC’s. In this talk, we will explore some challenges in designing and verification of Automotive SoC’s and how we can overcome these challenges with cadence solutions.

Lokesh Babu is the Director of System Verification Group at Cadence, having 16+ years of experience in Mobile and Automotive ASIC’s design and verification. Started Career at Texas Instruments (TI) as a Sr. Design Engineer and at TI worked on design and verification of High speed emulation chip and 802.11 a/b/g WIFI chips. In last 11+ year at cadence, driving System Verification Application Engineer team, primarily focused on new methodologies like Assertion based Formal Verification, UPF/CPF/1801 based Low power methodology, Automotive ISO26262 functional safety and security and Portable test and stimulus slandered (PSS).

 

Verification Flow for ASIL Compliant Automotive SoCs

 

Deva Phanindra Kumar, Design Verification Engineer, Analog Devices

Functional safety features are an essential part of automotive system-on-chip development. ISO26262 standard dictates ASIC development process in safety applications like airbag control, electronic stability control. This presentation focuses on verification requirements of ISO26262 standard. In this presentation, a verification flow and processes have been proposed which would meet stringent requirements of ISO26262. This presentation also covers verification challenges in verifying safety measures in the system and schedule budgeting tips for an Automotive ASIL compliant chip.

Deva Phanindra Kumar received M.Tech degree in Control systems and Instrumentation from the Indian Institute of Technology (IIT) Madras, Chennai, India in 2006. In 2006, he joined the Automotive Sensor Technology group at Analog Devices Inc, Bangalore, India. He is engaged in design and verification of signal processing electronics of sensors. His current research interests include Signal-processing, Mixed-Signal ASIC design and verification and Functional Safety.

 

Why you should Attend?

6 DVClubs held successfully over the past three years in collaboration with Cadence Design Systems.

 

Technical Benefits:

 

Learn the upcoming challenges in verifying & validating the Automotive chips

Budgeting tips for an Automotive ASIL compliant chip.

 

Verification Flow to meet the stringent ISO26262 requirement

Great opportunity to meet the like-minded people and network with industry experts.

Speakers & Participants from Tier 1 semiconductor companies like Cadence, Broadcom, Qualcomm, Volvo, Rambus, SanDisk, NXP, Infineon, and so on.

 

About DVClub India

The principal goal of DVClub India meeting is to have fun while helping build the Indian verification community through quarterly educational and networking events. Attendance at DVClub India meeting is free and is open to all non-service provider semiconductor professionals. Each meeting addresses a specific issue faced by the design and verification community and whatever your speciality provides an excellent opportunity for updating knowledge as well as share experiences, insights and issues with other members of the verification community.

 

T&VS are the coordinator for DVClub Europe and DVClub India events.

 

Methodologies for Rigorous Safety Verification

The next DVClub meeting in Europe is on 24th November 2017 and will be looking some alternative methodologies for performing rigorous safety verification. Read more

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