Breker Verification Systems forms Galactic Partner Program to accelerate Portable Stimulus Standard Ecosystem

May 2, 2018 ECD Staff

Breker Verification Systems today announced formation of its Galactic Partner Program, naming five inaugural consulting and training companies to help accelerate the Portable Stimulus Standard Ecosystem.

The inaugural partners are AEDVICES Consulting, Axiomise, Sunburst Design, Test and Verification Solutions (T&VS) and Willamette HDL, all recognized verification experts who manage and support large chip design and verification projects. Under terms of the program, each will work to build the ecosystem around the upcoming Accellera Portable Stimulus Standard, a standard means of specifying verification intent and behaviors reusable across target platforms, using the Breker tool suite.

Specifically, Sunburst Design and Willamette HDL will become Portable Stimulus Standard trainers based on the Breker tool suite, while AEDVICES Consulting, Axiomise, and T&VS will offer verification consulting services also based on TrekSoC and TrekUVM.

“As the Portable Stimulus Standard moves fully into the verification flow, it becomes critically important to have experts available to help further adoption,” states Adnan Hamid, Breker’s founder and chief executive officer. “We selected the best-known and regarded industry experts to train the users about the value and benefits of Portable Stimulus.”

Future announcements about Breker’s Galactic Partner Program will include new members who supply verification intellectual property (VIP) and tools. For more information about the Galactic Partner Program, visit: https://bit.ly/2GNUTNN

Breker first introduced a graph-based approach to test case generation in 2008, now known as Portable Stimulus. It gives chip design verification groups true Verification GPS (Graph-based, Portable, Shareable) with its Portable Stimulus solutions. Through the use of a Graph-based intent specification in an industry standard language, TrekSoC and TrekUVM offers proven Portability across verification platforms, scaling from IP to SoC for vertical reuse and SoC to post-silicon for horizontal reuse. It is Shareable across global diverse teams, project revisions and communication channels.

Breker’s tool suite is in use at large and mid-sized semiconductor companies worldwide on a variety of projects, including universal verification methodology (UVM) sequence synthesis and software-driven test generation from easy-to-author, graph-based representations and hardware/software scenario generation for emulation and system tests. Applications range from servers, networking, graphics processing units (GPUs) and field programmable gate arrays (FPGAs) to mobile and base stations for cellular wireless.

Breker is a founding member and an active participant of the Accellera Portable Stimulus Working Group (PSWG) and contributed a working C++ language representation for standardization efforts.

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