Aldec, a pioneer in mixed HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, will showcase its industry-proven Verification Spectrum for SoC FPGAs at Embedded World 2018.
Today’s SoC FPGAs present new verification challenges for system, software and hardware teams. Various issues related to HW/SW integration continue to increase, and yet they are only typically found in the FPGA testbed, which are costly to fix and often result to significant project delays. With Aldec’s 34+ year expertise in FPGA and ASIC verification, the Verification Spectrum is an end-to-end solution that provides best-practice verification methodologies, coding standards, integrated tools and FPGA prototyping boards that supports the Continuous Integration development flow.
Verification Spectrum to be showcased at Booth 4-560:
Mixed-Language RTL Simulator with Riviera-PRO - Supporting the latest VHDL, Verilog, SystemVerilog and UVM with 32/64-bit functional and timing simulation. Enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine with advanced debugging capabilities at various levels of abstraction. Integrated with FPGA vendor development tools such as Xilinx Vivado and Intel Quartus.
Design Rule Checking and CDC/RDC Analysis with ALINT-PRO - A design rule checking environment with a rich set of HDL coding standards for unit and chip-level linting. Focused on verifying RTL coding style, RTL and post-synthesis simulation mismatches, reliable and portable FSM descriptions, clocks and reset tree issues, clock domain crossing (CDC) and reset domain crossing (RDC) analysis.
Traceability Management with Spec-TRACER - Automates traceability creation from functional specification to SW and HW design source code, verification plan, testbench and test results. Traceability is a requirement for safety-critical applications such as DO-254 (avionics), ISO 26262 (automotive) and IEC 61508 (industrial).
HW/SW Co-Simulation Solution with QEMU and Riviera-PRO - System integration and simulation of FPGA custom IPs with software running on the SoC processor is simplified with the Aldec QEMU Bridge that connects open-source QEMU (co-emulator) and Riviera-PRO. The QEMU Bridge converts SystemC TLM transactions to AXI and vice versa providing a fast interface for HW/SW co-simulation. Such a solution helps the hardware and software teams to work together locate, identify, and fix bugs at an earlier stage in the development process.
SoC FPGA Prototyping Platform with TySOM - Small form-factor prototyping boards for embedded designers who require high-performance re-configurable SoCs for embedded vision applications (ADAS, surveillance and multimedia) and networking solutions.
The TySOM-3-ZU7EV features Quad ARM® Cortex-A53, Dual ARM Cortex-R5, UltraScale+ PL with Video Codec H.265/H.264, HDMI IN/OUT, 256MB NAND Flash, 4x USB 3.0, 2x FMC connector, QSFP+, Wi-Fi and Bluetooth.
The TySOM product line includes main Zynq boards, FMC daughter boards, advanced reference designs, tutorials and custom Linux that supports the Yocto Project.