Achronix Semiconductor Corporation has announced that it completed full silicon verification of its Speedcore eFPGA production validation chip built on TSMC 16nm FinFET+ process technology. Rigorous bench and ATE tests were completed across full operating conditions to verify the complete functionality of the Speedcore test chip.
Speedcore IP is a fully permutable architecture technology that can be built with densities ranging from less than 10,000 look-up-tables (LUTs) up to two-million LUTs plus large amounts of embedded memory and DSP blocks. Designed specifically to be embedded in SoCs and ASICs, Speedcore eFPGA IP enables SoC developers to design programmability into their devices to be a platform for their reprogrammable hardware accelerators, to address changing standards, or to future-proof their products.
The Speedcore silicon validation device was verified using the Speeedcore16t validation board, a platform available to potential customers to fully evaluate Speedcore eFPGA capabilities. Users have access to a number of application-specific reference designs that operate at 500 MHz and can be run through the companion ACE design tool suite to evaluate Speedcore capabilities as well as proof-of-concept exploration. A demonstration video can be found at bit.ly/2FIs5pt.