 | MIPS introduced their M14K and M14Kc lines today, with a couple of new wrinkles.They claim the new microMIPS instruction set keeps most of the performance while reducing code size by a bit more than one-third. Both devices are fully compatible with the regular MIPS ISA. Using the new ISA can cut system costs through reduced memory requirements.Along with a few other features, MIPS also took on one interesting feature that mostly gets overlooked: a flash accelerator block in the M14K.One of the first things programmers often do is copy code over from flash into RAM for faster execution. It seems most architectures just let this exist instead of fixing the weakness. MIPS is taking a shot at accelerating flash performance with some pre-fetch capability – we didn’t get a lot of details but it’s worth a closer look if you’re interested. Obviously, if you’re generating a whole lot of misses, this might not help and you might still have to shadow some sections of code, but the idea of being able to execute out of flash better is an interesting one.Also around these cores is extension capability. Optional units include CorExtend, which is a way to bolt in a co-processor in an SoC environment, and a User Defined Instruction (UDI) capability. Off core interfacing to peripherals is with the AHB-Lite interface.Lastly, there are the iFlowtrace extensions for debugging – something we’re about to have a viewpoint from MIPS on in our November print issue.These enhancements along with the new microMIPS ISA make this an interesting development.Topics covered in this article
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