The role of on-chip instrumentation has become much more important with high-speed signals, where off-chip instrumentation changes the picture when applied. This view of the concepts and differences is eye-opening.
Physical layer (PHY) standard interfaces for PCI Express and Ethernet are in the multi-GHz data rates. PCI Express 3.0 runs at 8 GTps, and 10GBASE-KR autonegotiates to just over 10 Gbps. At these speeds, probing at the package pin-out does not reveal the exact receive-side waveform. The package lead frame between the chip and the board electrically impacts the performance enough so that instrument suppliers try to model these effects to produce a better picture of the waveform as it exits the chip.
Such observability is important in optimizing the PHY block’s performance, not just to comply with the specification, but also to provide the cleanest eye opening. New high-speed oscilloscopes that can see these waveforms cost $100,000 or more. Although test bench time and expensive test equipment add to the inconvenience and cost of seeing what’s happening on the chip, they are crucial to making adjustments that ensure signal integrity and the best possible signal quality.
A precise and unobtrusive on-chip eye monitor provides visibility to receive-side data after equalization, offering an eye-opening view of the PHY’s performance. System designers look to such capabilities from their IP providers as a debug aid and a way to further optimize the receiver settings to improve performance.
What is an on-chip eye monitor, and how does it work?
This type of on-chip eye monitor is not a classic probe; it is a set of circuitry built into the design in a way that allows it to shadow the signals without affecting performance. Various on-chip eye-monitoring techniques have been developed and deployed in the industry.
For example, Snowbush IP uses a proprietary technique implemented in the decision feedback equalizer block. Implementing it here allows the circuitry to sample the actual signals used by the clock and data recovery function. The monitoring function performs in the normal operational mode in a nondestructive, data-independent manner in that it does not require any specific input data. But it can also work in a built-in self-test mode with any pseudorandom binary sequence or user-defined data pattern. The on-chip eye monitor samples the signal at the same point that the detection circuitry operates to adjust the equalization and then outputs a signal that allows designers to view a reconstructed eye diagram on a PC, representing the exact same signal the chip “sees.”
The on-chip eye feature allows the time axis (x) and the amplitude axis (y) to be swept (see Figure 1) and a corresponding Bit Error Rate (BER) to be calculated by comparing a roaming sample with the data sample. A BER measurement is made for each x and y offset. After sweeping x offset and y offset pairs, a BER-based eye is plotted.
Using software to program control registers, the monitoring circuitry reads the x and y offset sweeps and samples and then writes the BER measurement results for each corresponding point. The software can configure the resolution of the sweeps and the number of receive data bits. Once all of the data points have been captured, the software plots a 2D image color-coded based on the results. Figure 2 shows an example of an eye plot captured for 10 Gbps of data using x offset of 3 ps, y offset of 20 mV, and 562 receive data bits.
The software can also be configured to plot the gradient of the accumulated BER results. Using these results, designers can see the open eye in the BER eye plot, as well as the transitions and crossing points. Figure 3 shows a simulated eye on the right and the measured gradient plot of the eye on the left. The resolution of results is better than 2 ps in the time domain (x axis) and 2 mV in the voltage domain (y axis). The offset can be set to address the full horizontal eye opening; for the y offset (amplitude), the offset can be set to address ±150 mV (300 mV peak to peak).
What are the benefits?
Multirate PHY IP blocks used to support multiple standards, such as those offered by Snowbush IP, are electrically tuned to each standard. Using the eye-monitoring function, designers can see the results of that tuning capability adjusted to meet performance specifications on a variety of protocols, including Gigabit Ethernet, XAUI, RXAUI, Fibre Channel, SAS, SATA, USB 3.0 (SuperSpeed USB), and PCI Express. This enables designers to debug and optimize performance characteristics for interfacing to a wide variety of devices and protocols.
In today’s environment, the substantial increase in serial communications speeds, degraded channel characteristics due to higher data rates, sophistication of the equalization techniques used in receivers, and the high cost of test equipment require implementing new approaches to gain visibility into PHY performance. Whereas other alternatives are expensive and opaque, on-chip eye-monitoring techniques let the open eyes in a design be seen with precise clarity in a timely, cost-effective manner.
Kevin Walsh is director of marketing at Snowbush IP, based in Toronto, Ontario, Canada. With more than 25 years of experience in IP and EDA[
], he has an extensive background in marketing IP, including roles at inSilicon, Arasan Chip Systems, Synopsys, Fresco Logic, Sapphire Design Automation, and Simplex Solutions. He has a BS in Electrical Engineering and Computer Science from the University of California, Berkeley and an MBA from Pepperdine University.
Snowbush IP, a division of Gennum 416-925-5643 kevin.walsh@snowbush.com www.snowbush.com
