Plunify launches InTime optimization service to deliver FPGA design results in a day

February 6, 2018 ECD Staff

Plunify, supplier of field programmable gate array (FPGA) timing and performance software based on machine learning techniques, has announced immediate availability of InTime Service, a turnkey design optimization service for FPGA designs.

The service helps businesses achieve faster and more efficient FPGA applications in days with no upfront costs and no fees unless the desired target performance is attained. For most engagements, InTime Service is able to deliver results from between one to seven days, depending on design complexity.

“We eliminate risk and we’re fast,” affirms Kirvy Teo, Plunify’s vice president of business development. “Given enough time, any FPGA design can be optimized. We use machine learning and cloud computing to do it much faster.”

FPGA designers work on complex applications with challenging performance targets where each design is unique and requires effective design methodologies and tool expertise to attain the desired compilation results. With InTime Service, engineering groups engage Plunify to optimize their FPGA designs without changes in the register transfer level (RTL) code or constraints.

Plunify leverages its analysis and optimization algorithms to fine-tune synthesis and implementation processes to meet desired speed, area or power performance requirements. Its machine learning technology reuses parameters found to be effective for specific device families and designs, reducing the time needed to achieve performance targets for incremental changes.

In a recent example, a Fortune 500-listed scientific equipment maker used InTime Service to successfully optimize four high-end FPGA designs over five days, navigating failing slacks of up to -2.0ns in severity. The project manager Esteban Curiel confirmed the company’s satisfaction with the optimized results produced by InTime Service and the speed with which Plunify delivered them.

To learn more about InTime Service, visit bit.ly/2rzbXUl.

Previous Article
Hyperstone presents new API and more at embedded world 2018

Hyperstone GmbH will be exhibiting a newly developed API that allows developers to add their own extensions...

Next Article
Breker Verification Systems joins the ESD Alliance

Breker introduced a graph-based approach to test case generation that has formed the basis of the Accellera...

×

Follow our coverage of hardware-related design topics with the Hardware edition of our Embedded Daily newsletter.

Subscribed! Look for 1st copy soon.
Error - something went wrong!