RISC-V: Too Open to Fail

January 23, 2019 Brandon Lewis

CORRECTION: On 10/1/18, Arm announced a collaboration with Xilinx that made Cortex-M IP available for free through its DesignStart program.

Open-source RISC initiatives have, for the most part, failed to live up to expectations. OpenRISC, for example, introduced an ISA and architectural description for a family of 32- and 64-bit processors in 2000, but that resulted in only one implementation and limited adoption outside of academic circles. Another RISC-based open-source hardware project, OpenSPARC, has also had limited commercial success.

Therefore, it shouldn’t be surprising that optimism around the RISC-V ISA has been guarded. However, there are several cascading factors that make this particular open-source hardware technology too open to fail.

1. From Licensing Fees to Licensing “Frees”

With any free and open source technology, the first and most obvious reason RISC-V is attractive is cost. But what makes “free” particularly poignant in the case of RISC-V is the cost of alternatives.

This piece is not intended as a shot at Arm. However, at this point it is common knowledge that licensing even the simplest Arm Cortex-M0 CPU cores for commercial use can cost thousands of dollars or more up front, with a 1-2 percent royalty charge added for every chip sold. In response, Arm launched a program called DesignStart to offset those upfront licensing costs for qualified participants.

But based on feedback from customers, Dan Ganousis of RISC-V IP provider SiFive and formerly of Codasip says “the total cost of an -M0 DesignStart license when royalties are included is a minimum of $370,000 upfront” because, according to him, Arm values royalties at a minimum of $330,000.

Figure 1. Dan Ganousis' interpretation of Arm DesignStart pricing.

Of course “free” anything is never really free at all, as you have to account for the extra development work associated with the RISC-V ISA and any of the derivative cores that have been open sourced.  Then again, smart people can make $370,000 go a long way.

Under the new structure of Arm's DesignStart program, according to Arm, all upfront costs are now waived for qualified participants using Cortex-M0 and Cortex-M3 IP. These users begin paying royalties after tapeout when product begins to ship.

Figure 2. Updates to the Arm DesignStart program waive all upfront licensing costs for qualified DesignStart members. According to the company, royalties can be less than $100,000 for a Cortex-M0-based device in 5 million unit quantities.

Keep in mind, though, this only applies to qualified participants, and royalties for the DesignStart Pro license kick in after 1,000 units. After that it's a numbers game, and because there are so many costs associated with developing a chip, it can get sideways quickly.

2. No More Mr. Moore, More M&A, and Sand Hill Road Stays Dry

When considering the groundswell of support for RISC-V, it’s important to note that several related industry trends are contributing to its success. One that shares a direct link with IP licensing costs is that Sand Hill Road just isn’t swiping the platinum VC card for semiconductor startups anymore.

How could you blame them? The cost of developing even the most rudimentary chip starts at around $1 million when you factor in hardware and software engineering, IP licensing, tools, tapeout, and testing. And, that’s before you get to chip production, which requires silicon, packaging, assembly, another round of testing, and, of course, the aforementioned royalties.

Meanwhile, Arm and x86 architectures have dominated major electronics markets for so long that there is little room left for innovation. In the embedded space, every major chip vendor offers basically the same portfolio of Arm-based processors with a specialized core here or there and different smatterings of peripherals. Moore’s Law, the foundation of Intel’s x86 business strategy, is over. If you’re looking for proof, look no further than the more than $250 billion in semiconductor M&A activity since 2015. Some of these have been multi-billion-dollar deals designed to keep shareholders happy in the near- to mid-term, while many others have been fliers on startups in perceived growth areas. Neither is a sign of notable organic innovation.

Figure 3. Semiconductor mergers and acquisitions, 2010-2018 (Source: IC Insights).

Each of these trends signals an industry ripe for lower barriers to entry and a reimagining of the status quo.

3. The “Nation State” Processor

Every advanced economy in the world today is rooted in electronics. Even if high tech isn’t one of the country’s leading industries, virtually every sector – from communications, finance, and healthcare to energy, manufacturing, and transportation – is based on capabilities enabled by electronic systems.

It is therefore in the interest of these governments to protect their electronic capabilities, both now and in the future. One way of ensuring this is to reduce dependence on foreign technology and bring the electronics development onto domestic soil. In the event of extended trade wars or something worse, electronic self-reliance can be the difference between a position of weakness and a position of strength.

For years, the Indian government has funded the development of six 32- and 64-bit RISC-V CPUs at the Indian Institute of Technology Madras and Center for Development of Advanced Computing. In fact, Krste Asanović, Chief Architect and Co-Founder of RISC-V IP company SiFive and one of the original developers of the ISA at U.C. Berkeley says the country has “decided on RISC-V as national ISA for India.

The open-source instruction set also has a large following in China.

Too Open to Fail

Given the number of solid architectures that have faded into the history books, sometimes the stars have to align for a technology to be successful. For some, RISC-V is the answer to Arm that Arm was to Intel, or, in the software context, what Linux was to Windows. For others, it offers a new path towards innovation. For others still, it can provide insurance against turbulent political and economic times.

Whatever the reason, RISC-V is too open to fail.

Next we'll examine why RISC-V is too open to succeed.

About the Author

Brandon Lewis

Brandon Lewis, Editor-in-Chief of Embedded Computing Design, is responsible for guiding the property's content strategy, editorial direction, and engineering community engagement, which includes IoT Design, Automotive Embedded Systems, the Power Page, Industrial AI & Machine Learning, and other publications. As an experienced technical journalist, editor, and reporter with an aptitude for identifying key technologies, products, and market trends in the embedded technology sector, he enjoys covering topics that range from development kits and tools to cyber security and technology business models. Brandon received a BA in English Literature from Arizona State University, where he graduated cum laude. He can be reached by email at brandon.lewis@opensysmedia.com.

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