Green in: SoC hibernates, multicore sleeps deep, and kit manages power programmably

September 1, 2009 OpenSystems Media

In our Deep Green Editor's Choice section, we look at technology helping design green into today's new products.

A unique System-on-Chip (SoC) with very low voltage operation, a dual-core processor with advanced standby capability, and a processor power management development kit are this month’s top picks.

SoC goes to 0.5 V

One way to cut power is to operate at a lower voltage. Most SoCs give up around 1 V, but Cypress Semiconductor has taken their new PSoC 3 and PSoC 5 parts down to the unheard of level of 0.5 V with an incredibly low standby power rating.

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Figure 1

What would a programmable device with an 8051 or ARM Cortex-M3 core offering a hibernate mode consuming 200 nA do for some ultra-low-power applications? Read more about these devices in our ECD blog and see for yourself.

Cypress Semiconductor
www.cypress.com
RSC# 42994

Deep sleep backed by dual core

Many pieces of gear call for a fair amount of processing power, but only when it’s required. The rest of the time, the processor can literally nap while waiting for a job to arrive. Applications such as printing and backup storage devices meet this kind of profile.

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Figure 2

Freescale Semiconductor’s latest QorIQ P1022 device integrates dual Power Architecture cores running from 600 MHz to 1 GHz along with PCI Express, SATA, SD/MMC, Ethernet and IEEE 1588, USB, an LCD controller, and more. The processor cores can operate independently in advanced media processing applications. The device also incorporates Jog technology, which lowers power consumption dynamically based on workload, and offers network-aware, packet-lossless, deep-sleep capability. Freescale claims network standby operation of 1 W, making the device ready to respond to packets instantly.

Freescale Semiconductor
www.freescale.com
RSC# 42995

Development kit for power management

Three key support functions handle normal processor power management: a voltage supervisor, a watchdog timer, and a reset generator. While these functions are fairly common, different systems require programmable logic to implement the management logic needed to meet the conditions.

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Figure 3

The ProcessorPM Development Kit from Lattice Semiconductor features a ProcessorPM-POWR605 device along with a Power Manager II-POWR6AT6 preconfigured in a demonstration design that can be programmed using PAC-Designer software. Connecting the board to a host via USB allows designers to simulate and design a complete power monitoring and management circuit for MCUs, DSPs, and FPGAs.

Lattice Semiconductor
www.latticesemi.com
RSC# 42996

Don Dingee (Editorial Director)
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