Using emulation to verify today's complex designs

June 1, 2010 OpenSystems Media

2System-on-Chip designs aren’t getting smaller, so the verification strategy has to get faster to deal with complexity and obtain solid results in an acceptable amount of time. Emulation presents one verification method that can do this.

Such multilevel debugging methodology would not be possible with software simulators because they are too slow to effectively execute embedded software. Likewise, the same methodology would not be possible with FPGA-based prototypes since they lack visibility and access into the design to trace hardware bugs.

New emulation platforms

New emulation systems (Figure 1) are now replacing traditional big-box versions because they run faster and are easier to use and less expensive. They also consume a fraction of the power dissipated by bigger versions, require less space, and weigh less.

21
Figure 1: New cost-effective emulators offer performance, debug capabilities, and design capacity to make them ideal for today’s large SoC designs.

These highly scalable, cost-effective tools are capable of handling up to 1 billion ASIC gates, boast fast compile time and emulation speed, offer a powerful debug environment, and support multiple concurrent users, all packaged within an environmentally friendly footprint.

What’s more, emulators can be deployed as emulation systems driven by a physical target system or as acceleration systems driven by a virtual, software-based test bench. Typical performance is approximately 10 MHz on a 10 million gate design and a top speed of 30 MHz on smaller designs. In these examples, emulators would process 10 seconds of real time in less than two minutes. Fast compile times range from 5 to 30 million gates per hour on PC farms, depending on the size of the farm and the design’s complexity.

Increasing time-to-market pressures, along with escalating hardware/software integration and quality concerns imposed on engineering teams, make the verification process a strategically important step in chip design. A new generation of cost-effective emulators such as EVE’s ZeBu-Server (for Zero Bugs) capable of handling up to 1 billion or more ASIC gates at high speeds reaching several megahertz provides a great choice for large designs.

Lauro Rizzatti is general manager of EVE-USA. He has more than 30 years of experience in EDA and ATE, and has held responsibilities in top management, product marketing, technical marketing, and engineering.

EVE-USA
408-457-3201

lauro@eve-usa.com
www.eve-team.com

Lauro Rizzatti (EVE-USA)
Previous Article
Static analysis aids code portability

Static analysis tools help developers ensure that porting will proceed as planned.

Next Article
Green in: Two CPUs at 1 W and a batteryless wireless sensor module

In our Deep Green Editor's Choice section, we look at technology helping design green into today's new prod...