Understanding analog IP cores for embedded computing needs

October 1, 2012 OpenSystems Media

2Understanding and selecting analog IP can be risky, but engineers today have more choices and more control than they think. Knowing how to manage the IP selection process can help engineers effectively meet objectives and reduce risk.

As digital design has proliferated the electronics world, making designs faster, easier to test, and more robust, the analog portion of embedded designs is becoming a bottleneck. To meet requirements and timetables in the analog portion, engineers generally have three weapons at their disposal: utilize peripheral analog IC, build the functionality internally (make), or purchase the IP block from an external vendor (buy). Each option has its own merits and drawbacks, but none can launch a competitive advantage better or cause more frustrating confusion than analog IP.

Traditionally, these options only apply to ASIC builds, as FPGAs are not compatible with analog IP. However, this is changing quickly. Some IP companies now provide all Register Transfer Language (RTL)-based Analog-to-Digital Converter (ADC), Digital-to-Analog Converter (DAC), DC-DC converter controller, and clocking functions with robust performance.

To meet design objectives, engineers must understand the IP vendor’s strategy and incentives and match their offerings to what is required. The following discussion provides a robust roadmap for understanding the analog IP landscape as well as evaluating and selecting analog IP.

Analog IP landscape

The analog IP market has exploded in the past 10 years. Demand for ADC, DAC, Phase-Locked Loop (PLL), and DC-DC converter IP is expected to grow at more than 17 percent through 2015, according to Semico. Two forces are largely responsible for this. First, the amount of analog talent in the labor pool has reduced dramatically. Second, competitive pressures are putting premiums on time to market and costs. IP is seen as an effective strategy for meeting time to market and addressing significant bottleneck issues because it allows engineers to purchase blocks and amortize the cost over multiple projects.

Strategy + business model

Analog IP firms invest heavily in R&D to lead on the performance front and then market those products for a variety of applications. The model works great for innovation and for customers needing state-of-the-art performance. Performance premiums are often not necessary for the application. This is where proper requirements definition comes in handy.

Most analog IP firms charge upfront license, per-unit royalty, and related maintenance and service fees. Licenses can usually be expanded from single use to multisite to amortize costs more efficiently (see Figure 1).

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Figure 1: An analog IP business model allows engineers to purchase blocks and amortize the cost over multiple projects.

Analog IP challenges

Because analog IP blocks are usually delivered as hard macros, they are largely dependent on process technology and are difficult to modify and test. This decreases the number of options and can make a customer more reliant on a specific foundry. Analog IP companies are exerting a great deal of effort to migrate their portfolios to smaller technologies, but are seeing major challenges at 40 nm and below. This has long-term implications for product roadmaps as costs grow exponentially at smaller technologies. These challenges present strategic trade-offs for embedded teams.

When ADC, DAC, or DC-DC controller IP is developed in all-digital RTL, many of these challenges are removed. All-digital ADC cores, for instance, are easily modified for special requirements, technology independent, FPGA embeddable, and digitally testable. These cores are often smaller and lower power due to the use of a digital fabric. The drawback of this approach is limited resolution and bandwidth. At Stellamar, ADCs currently offer up to 16-bit resolution and 400 kHz bandwidth. By comparison, analog ADCs offered in mixed-signal FPGA packages provide 12 bits and 500 kHz bandwidth.

Steps to evaluate IP/system fit

With a high-level understanding of the analog IP landscape, engineers can concentrate on avoiding the two most common problems when selecting IP: unclear objectives and improper requirements definition. To do this, a team considering buying IP must thoroughly understand these two dynamics.

Project objectives

Given the trade-off of offering smaller technologies at higher costs, clarity on the most important overall project objectives is critical. Analog IP is one tool of many that can help engineers meet an objective, and whatever tool is chosen dictates how the team allocates resources to meet the objective.

One of the best tools for prioritizing objectives is the CARVER matrix that Navy SEALs use to assess the value of a military target in a quick, no-fail way. This exercise can shed light on the most important issues to the design team, including reuse versus custom, foundry reliance, and technology portability and prototyping. Try this exercise in a group or individually to compare how team members view objectives.

First, list critical objectives for the embedded design project. Be specific. Objectives such as low power and small area aren’t nearly as effective as actual numbers. Objectives should also include higher-level strategies such as “foundry neutral” or “ensures process roadmap.”

Next, score the objectives 1-5 (5 being highest) on each of six criteria:

  • Criticality: How critical is this objective?
  • Accessibility: How achievable is the objective with internal resources? Purchased IP?
  • Recognizability: Does the team recognize the objective as important?
  • Vulnerability: What force is needed to achieve the objective? Can it be achieved in a certain time frame? Are large amounts of resources needed?
  • Effect on mission: How much closer does this objective get the design to meeting the overall strategy?
  • Return on effort (ROI): How much bang for my buck?

Table 1 shows an example CARVER matrix.

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Table 1: A CARVER analysis can shed light on an IP project by rating the importance of design objectives according to six critical factors.

In this example, the team’s overall strategic objectives are to limit reliance on one foundry and ensure the IP can get the product to 22 nm. These objectives are achievable in the current IP landscape if technical requirements can be met, leading to the next dynamic of understanding.

Technical requirements

In the old days of in-house IP development, engineers would gather requirements and build IP blocks exactly according to those specs. This often increased cost, lead times, and risk when targeting a new technology. As cost and time-to-market pressures have transferred IP production to the “outhouse,” adherence to specifications has relaxed. This benefits IP companies who market their higher-performance blocks for wide-ranging, lower-performance applications.

A vendor has limited ability to meet specific requirements in a given budget or time frame. Foundry and process portability challenges further limit optimal choices for the customer. These limits have ramifications from higher power consumption to price premiums for unnecessary performance. Proper requirements definition is key to understanding where trade-offs will occur and how those trade-offs can be counterbalanced.

To start proper requirements definition, some key questions need to be asked, including:

  • What is being measured, and what is needed?
  • What are the minimum resolution and bandwidth needed to completely convert the input?
  • What are the power and size budgets?
  • What are the input characteristics?
  • Are there unique timing needs?
  • Is the prototype system FPGA-based?
  • How can the design convert from FPGA to ASIC?
  • What foundry created the IP? What process was used?
  • What are the test requirements?

Standards exist for many functions. For instance, audio is still 12 bits and 15 kHz bandwidth. Professional audio is higher, and knowing this difference can save money and time. As another example, many DC-type measurements have very small bandwidth, often sub-10 Hz, yet engineers often choose ADC IP with greater than 1 MHz bandwidth because of availability. This is like using a sledgehammer to drive the head of a pin. It gets the job done, but will consume more power than necessary. Similarly, integral and differential nonlinearity degrades the effective number of bits for some ADCs. If the requirement is 12 bits, a 14-bit ADC block might be needed to achieve the required 12-bit resolution.

IP selection

Armed with prioritized strategic objectives and exact technical requirements, the team can start the selection process. Websites such as Chipestimate.com and Design-reuse.com are good places to start. Xilinx and Microsemi also provide robust IP ecosystems that include analog IP functions from providers like Stellamar.

To attain the level of comfort needed to make a selection, the team must ask the vendor a number of questions, including:

  1. Does the vendor have customers and success stories?
  2. Are the cores silicon-proven?
  3. What level of support is provided?
  4. Can the core be evaluated before purchase?
  5. What deliverables are provided?
  6. What is the licensing structure?
  7. How long will it take to tailor IP to specific needs?
  8. How long has the company been providing IP cores?
  9. How free is the company with sharing basic information?
  10. What strategic partnerships does the vendor have?

By following this roadmap in sequence and asking all of the important questions, the design team should be confident that third-party analog IP selection and integration can help meet strategic objectives and add significant value to the overall system design.

Allan Chin is CEO of Stellamar.

Stellamar allan.chin@stellamar.com www.stellamar.com

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Allan Chin (Stellamar)
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