Transaction-level modeling brings IP up to speed

May 24, 2017 OpenSystems Media

3As a complete alternative to developing in register transfer level, transaction-level modeling can form the "golden source" for systems-on-chip and provide benefits in verification speed and quality. Here's an overview of transaction-level modeling and its benefits.

System-on-Chip (SoC) development costs continue to grow rapidly, driven by increasing demand for more functionality, device mobility, and improved usability. These new capabilities demand more sophisticated software executing on multicore hardware and other special-purpose accelerators to meet power and performance requirements. Design team productivity has not kept up with this growth in complexity, leading to lengthening development schedules. Because of this and other factors, development costs for complex SoCs are approaching $100 million, requiring companies to sell tens of millions of units to return a profit on that investment.

The task of developing and integrating low-layer hardware-dependent software is usually on the critical path in systems projects and has the highest potential to reduce project costs. The problem is that software development often doesn’t begin until detailed and verified hardware models are available, and even those models might not fully meet system requirements. Software/hardware integration occurs at the end of the project, when changes are expensive and lengthy to implement. The fixes are often limited to software, leaving the hardware suboptimal or omitting critical capabilities.

Functional verification of hardware and software and their interactions is another task on the critical path of a systems project. The increasing range of functionality in SoCs and software is raising design complexity and exponentially driving up functional verification costs. In addition, most current design processes capture the design as a Register Transfer Level (RTL) description, which is a somewhat detailed format that makes changes difficult to implement and slow to verify. Many bugs are discovered toward the end of the schedule, requiring costly iterations to fix and reverify the system.

Industry support is growing for the use of Transaction-Level Modeling (TLM) as a way to parallelize hardware and software development and to speed the path from design to silicon. Despite the widespread industry interest in TLM, creation of a standard approach to developing truly interoperable IP using TLM has been stalled by differing approaches. Overcoming the differences and defining a unified methodology for SoC IP interoperability can address the new reality of tighter interdependence between hardware and software, allowing semiconductor companies to significantly reduce risk and cost.

An automated approach to IP creation

Hardware virtual prototypes and high-level synthesis offer significant benefits for system design, but they remain largely disconnected because they use different hardware models. Creating a single TLM model for virtual prototyping, IP synthesis, and functional verification eliminates the duplicated effort and software quality problems that can occur if the models differ.

Virtual prototypes combine special-purpose processor models with TLM models of the design IP to provide a platform for developing hardware-dependent software drivers (shown in Figure 1). The TLM IP models provide an accurate representation of the hardware and serve as the single source for high-level synthesis to RTL.

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Figure 1: Virtual prototypes provide a platform for developing hardware-dependent software drivers by combining special-purpose processor models with TLM models of the design IP.

High-level synthesis has matured as an enabling technology and can now support most common hardware structures, making it possible to develop an entire SoC using TLM as the “golden source.” The fewer lines of source code correlate with fewer bugs. Simulation is faster at the higher level of abstraction, so functional verification schedules are shorter, which means bugs are found earlier in the project.

Furthermore, a single, reusable functional verification environment can be built for both TLM and RTL. This reduces the cost of reusing IP because the high-level synthesis tool can map the TLM description to new architectures. Also, a high-level synthesis tool that automatically integrates engineering change orders can rapidly implement late bug fixes or minor requirements changes.

After cleanly separating system constraints from the high-level logic design source code, the IP can be reused for new architectures by changing the synthesis constraints. The abstraction and automation multiply the productivity of engineers who are creating the logic. However, the full benefits of high-level synthesis cannot be achieved with a flow that simply produces RTL and uses the current RTL-to-GDSII flow. The TLM implementation flow must optimize the complete process, from reading the TLM through producing the resulting layout.

Functional verification requires an automated approach to explore corner-case behaviors of the design and increase the productivity of verification engineers as they specify the enormous range of system operating conditions. The Open Verification Methodology (OVM) is an industry-standard verification methodology for both TLM and RTL designs. Leveraging the OVM, design teams can define a verification approach that minimizes the effort required to migrate the verification environment from TLM through RTL and reuses code throughout the process. Metrics that measure the functional behaviors of the design can focus the verification effort on those system behaviors not yet observed instead of repeating previous coverage. Debugging can be integrated across all levels of abstraction and ideally be correlated to the original TLM source that the engineer created.

To achieve all of these benefits, a new IP modeling methodology is needed to unify early software development and hardware design. The methodology must enable the creation of TLM models that support early software development, functional verification, and high-level synthesis, while integrating with the existing RTL methodology infrastructure. A single model reduces the effort as well as the bugs introduced during coding. As this methodology becomes more widely adopted, it is defining new opportunities to reuse IP within the overall enterprise and transforming the third-party IP ecosystem.

New TLM IP categories

The emergence of TLM-based virtual prototyping, synthesis, and functional verification solutions will define a new set of IP categories. Each category is part of the overall design flow and provides opportunities for reusability within a company as well as third-party IP businesses. A unifying methodology must incorporate all of the following IP types to enable a full TLM solution:

  • Functional design IP: Computation (not interface or bus) logic, typically for synthesis
  • Virtual prototype IP: Computation (not interface or bus) logic for developing software
  • Synthesis constraint IP: Area, timing, power, and other guidance to a synthesis tool
  • SoC estimation IP: Area, timing, and power characterization for chip-level estimation
  • Functional transactor IP: Bus or interface of pin-level model for virtual prototypes and synthesis
  • Synchronization transactor IP: Synthesizable model for communication between two IP blocks
  • Verification IP: Code that models external drivers, checks correctness, and measures completeness
  • Verification plan: Stages of verification and metrics to measure successful completion

Industry IP trends

As a first critical step, the industry is standardizing on TLM using SystemC to represent system hardware and enable broad adoption of virtual prototype model development. Other emerging standards use TLM to model hardware intended for synthesis and standards to define reusable test benches for functional verification across multiple levels of abstraction. The goal is to align all of these methodologies and IP types and enable the creation of a single hardware model that supports early hardware and software development as well as higher-productivity system integration and verification (shown in Figure 2).

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Figure 2: A single hardware model must combine standardized methodologies and IP types to support functional verification across multiple levels of abstraction.

IP reusability is the main driver for a unified methodology. Years ago, a unified definition of RTL reuse expanded the opportunities for companies to form around IP. For TLM IP, the goals of IP reuse are a superset of RTL IP reuse. The IP needs to support transaction-level virtual prototypes for early software development, high-productivity design flows using high-level synthesis to explore different architectures, and advanced functional verification of the TLM and the SoC that integrates the TLM IP.

Exploding system development costs and shrinking schedules are driving the industry to adopt TLM, a new level of abstraction that enables earlier software development and more productive hardware design and implementation. The transition to this new abstraction will strengthen the IP industry by offering new capabilities and reducing maintenance costs. TLM should be embraced as an opportunity to add much higher value to IP offerings.

Steve Brown is director of product management and system development automation at Cadence Design Systems. His experience includes several senior-level engineering and marketing positions at Cadence, Verisity, Synopsys, and Mentor Graphics. Steve earned BSEE and MSEE degrees from Oregon State University and studied business leadership and marketing strategy at Stanford, Berkeley, Harvard, Kellogg, and Wharton. He teaches a Silicon Valley business leadership continuing education program at the UC Santa Cruz extension.

Cadence Design Systems 408-943-1234 www.cadence.com

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Steve Brown (Cadence Design Systems)
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