Rising to the USB 3.0 challenge: smart design achieves high-speed signal integrity

April 1, 2011 OpenSystems Media

4A particularly tough game of tug-of-war may come to mind for engineers confronted with the rigorous technical specifications of an ultra fast data link that is backward compatible to much-lower-speed predecessors. Alexander describes an approach to meeting these challenges.

The long predicted convergence of the computer and consumer electronics industries has arrived. Driven by increasing consumer use of large digital music libraries, digital image files, and high-definition video, we are seeing a new generation of technology standards reach the market. One such standard is the Universal Serial Bus (USB) 3.0 specification, which features a SuperSpeed data transfer rate of nearly 5 GBps.

At CES 2011, the USB Implementers Forum announced that 165 USB 3.0 devices had been certified, representing a tenfold jump from the number of certified devices just one year earlier. And the market forecast firm InStat predicts that by 2013 the number of SuperSpeed USB devices shipped will reach one billion (25 percent of the total USB market).

USB evolution

Introduced in 1996, USB hit the streets with data rates of 1.5 Mbps in Low-Speed (LS) mode and 12 Mbps in Full-Speed (FS) mode. In 2000, USB 2.0 added a High-Speed (HS) mode operating up to 480 Mbps and remained downwards compatible to both the LS and FS modes.

The USB 3.0 specification released in November 2008 supports all USB 2.0 modes (HS, FS, LS) and the new SuperSpeed 5 Gbps data link. The SuperSpeed link works with separate differential data lines for download (Host => Device, called TX direction) and for the upload in RX direction (Device => Host). See Figure 1.

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Figure 1: USB3.0 – Physical link including ESD protection at the host and at the device.

The combination of USB 2.0 functionality and the new SuperSpeed mode requires a new cable construction to serve three differential coupled signal lines (TX+/Tx-, RX+/Rx-, and D+/D-), along with a Vcc and GND line. Serving a high cutoff frequency without interaction between the adjacent differential coupled line pairs presents yet another design challenge.

Designers need a new connector shape to handle all of these lines, one compatible with the USB 2.0 connector. Close proximity of the lines results in a high probability for Elecrostatic Discharge (ESD) strikes on the SuperSpeed lines at the host and at the device.

Ultra-high-speed data transmission systems also require high Signal Integrity, especially at the receive side. Thus it is important to achieve a low bit error rate (for example, a USB 3.0 SuperSpeed bit error rate of 10-12 is typical).

In a perfect system without limitation in bandwidth an eye diagram measurement of Signal Integrity would be perfectly open. In a real system, the TX and the RX impedance in combination with parasitic capacitance at both cable ends (either inside the USB 3.0 transceiver and/or externally on the PCB) limits the signal rise/fall time. External parasitics can be caused by unmatched PCB lines, the USB 3.0 connector, or other shunt capacitors. The low pass frequency response of the USB 3.0 cable also has to be taken into account. Changing the signal by a dedicated equalization on the TX and RX side compensates for attenuation of the high frequency content.

The SuperSpeed and the USB 2.0 transmission link work with differential coupled 90-Ohm lines. Signal reflections caused by impedance mismatch inside the link have an impact on Signal Integrity. To avoid this the entire layout, including the USB 3.0 cable, should be impedance matched to 90-Ohm differential.

To keep the “impair skew” as small as possible and match electrical delay, all differential coupled lines (including those in the USB 3.0 cable) have to have the same length. High impair skew leads to common mode signal generation, which can cause problems for EMI testing. Signal Integrity will suffer as well. A proper impedance matched layout can avoid these issues.

Layout considerations for the USB 3.0 SuperSpeed and USB 2.0 link

Key design considerations for the entire USB 3.0 link include:

  • Fully impedance matched 90-Ohm differential design approach for all PCB lines and interconnection cables.
  • NON-differential coupled lines should be minimized, as they have significant impact on the opening of the eye pattern.
  • A line width of 0.3 mm and a line gap of 0.2 mm between the differential lines are desirable to minimize loss and be robust enough for PCB manufacturing. Dielectric height would be 0.2mm (FR4, er=4).
  • Minimizing impair skew by identical delay (line length) between the positive and the negative line (including the USB 3.0 cable) of the differential coupled link.

ESD protection for USB 3.0

SuperSpeed USB operates at a fundamental frequency up to 2.5 GHz. For high Signal Integrity, rise and fall time of the data signal has to be very fast. The 3rd or even the 5th harmonic has to be handled without significant attenuation. What’s required is a state-of-the-art semiconductor process to minimize parasitic effects to achieve fast switching times. The drawback of these miniaturized semiconductor structures is the weakness regarding overvoltage caused by an ESD strike. ESD prevention with on-chip ESD protection causes parasitic effects (parasitic capacitances), adds expensive chip area, and will never reach system-level ESD performance.

A very cost-effective approach is to combine an internal ESD protection structure (integrated in the USB 3.0 transceiver) with a robust, high-current application circuit for external ESD protection implemented on the PCB. The internal ESD protection structure enables device level protection (for example, HBM JEDEC JESD 22-A115), which is important for device handling during development, production, and board assembly. The external ESD protection provides system-level ESD protection according to IEC61000-4-2.

For proper USB 3.0 system-level ESD protection, the ESD protection device (TVS diode) has to handle the majority of the ESD current and keep the clamping voltage as low as possible. The residual ESD stress visible for the subsequent device has to be within the limits stated for this device.

The relevant TVS diode characteristics are:

  • Lowest Ron (Rdynamic)
  • Lowest Vbreakdown, but tailored to the application

A rule of thumb for Vclamp (no snapback effect): Rdynamic can be extracted by Transmission Line Pulse (TLP) measurement (Figure 2).

22
Figure 2: TLP result for the Infineon ESD3V3U4ULC dedicated for USB 3.0 SuperSpeed ESD protection.

For a safe application, Vbreakdown has to fit with the maximum applied signal level on the protected lines. Lowest Rdynamic in combination with optimized Vbreakdown keeps residual ESD stress for the IC minimized.

Infineon produces an application tailored TVS Diode (ESD3V3U4ULC) to meet the requirements for USB 3.0 SuperSpeed ESD protection. It has an Rdynamic of only 0.2 Ohm (typ.) and maximum reverse working voltage of 3.3 V (Vbreakdown: 5 V min).

Clamping voltage for a 16 A ESD strike shows 9 V, which is a best-in-class result. Diode capacitance (diode versus GND) is 0.4 pF typical. ESD handling capability exceeds 20 kV without any degradation. The 16 A TLP test pulse fits very well to an 8 KV contact ESD strike according to IEC61000-4-2, providing an ESD current of 16 A @ the 30nsec point.

To complete the system design, separate TVS diodes are required to protect the additional USB 2.0 link. These diodes have to provide a slightly higher reverse working voltage/breakdown voltage to handle the Full-Speed and the Low-Speed mode. The Infineon ESD5V3U1U and ESD5V3U2U series serve a minimum reverse working voltage of 5.3 V (Vbreakdown: 6 V min) and a diode capacitance of 0.4 pF typical.

Simulation results

Signal Integrity simulations of the entire USB 3.0 SuperSpeed link (Figure 1) with and without ESD protection were performed, based on the specification and layout rules described above. The USB 3.0 cable was specified to maximum three-meter length. TVS diodes were placed at the host and at the device side.

For simulation, Infineon implemented TX de-emphasis and RX-equalization according to the USB 3.0 compliance test standard parameters. The eye pattern (Figure 3) of the SuperSpeed signal was checked after the RX equalizer. The simulation was performed for 106 bits. The eye diagram was extrapolated to 1012 bits and run both with TVS (blue line) and without the TVS diode (red line).

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Figure 3: Eye diagram w. (blue) and w/o. (red) TVS Diode located at host and at device side.

The degradation in eye pattern opening is very small. Yet at the same time this approach affords a huge safety margin with respect to the USB 3.0 specification mask (magenta line).

Summary

Successful USB 3.0 design requires both error-free Signal Integrity and excellent system-level ESD performance. To meet these requirements, the ESD protection device must provide excellent ESD performance and a very low device capacitance. This can be achieved using the Infineon ESD3V3U4ULC in “array” configuration combined with a clear and straightforward layout and high link quality (USB 3.0 cable).

Alexander Glas is a senior staff engineer at Infineon’s RF Protection Device group. He has been working in various positions in RF research, development, and technical marketing for 20 years. Alexander holds an electrical engineering degree granted by the Technical University of Munich.

Infineon Technologies www.infineon.com

Alexander Glas (Infineon Technologies)
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