Emulation tools reinvigorate power analysis in large SoCs

July 11, 2016 OpenSystems Media

In the new power electronics era, where higher-power switches are being integrated into large system-on-chip (SoC) designs, the traditional methodologies are being replaced with more complex structures. That inevitably adds to design complexities, and here, the next-generation emulation tools can help designers with more detailed and accurate predictions of the power usage at the system, RTL, and gate level.

The advent of the FinFET process technology has brought major improvements in the static leakage; however, dynamic power is still a major concern in chips for smart devices as well as data centers. So a new model is emerging that plots the switching activity during the emulation and passes the information to power analysis tools.

1. Traditional power analysis comprises of a file-based flow being carried out in two steps. 1. Traditional power analysis comprises of a file-based flow being carried out in two steps.

The traditional approach for power estimation employs a file-based flow that’s fed to the power-analysis tools. A simulator or emulator tracks the switching activity either in a switching activity interchange format (SAIF) file or in a signal database file like FSDB or VCD. These files are fed to a power-estimation tool to find out average and peak power uses.

This approach worked well for smaller chips with a few million gates, but for bigger SoC designs, files become unmanageably large. So the power estimation tools would take a long time to read and process these files and sometimes could not process large files.

Replacing file-based flow

Mentor Graphics’ Veloce emulation systems allow engineers to accurately predict power consumption in large chips, first by eliminating the two-step file-based flow and then tightly integrating the emulator with the power-analysis tool.

The Veloce Power Application—aided by the actual OS and application behavior—identifies and zooms switching activities that are generating power peaks. It even includes identification of switching-activity time frames that may threaten the power design. And unlike file-based power charts, which could consume more than a week to generate an activity plot of a 100-million gate design, Veloce would take just 15 minutes to carry out the task.

The next phase in power design is to find out where these peaks are happening in the chip design and what’s causing them. Enter the Dynamic Read Waveform API that replaces the current SAIF/FSDB/VCD file-based methodology with live streaming of switching data from the emulator to the power estimation tool. The switching data is supplied directly to the power-analysis tool (PowerArtist from Ansys) instead of being delivered via a file.

2. Mentor's Veloce emulator delivers accurate gate-level power analysis by integrating Dynamic Read Waveform APIs with power analysis tools. 2. Mentor’s Veloce emulator delivers accurate gate-level power analysis by integrating Dynamic Read Waveform APIs with power analysis tools.

Collectively, Veloce Power Application and Dynamic Read Waveform API facilitate a more efficient power analysis at the system level, one that’s otherwise not possible with a file-based flow. Case in point: the early users of Veloce’s emulator integrated with power analysis runtimes have witnessed a 5 to 10X performance improvement. That’s powerful.

Jean-Marie Brunet Marketing Director for the Emulation Division at Mentor Graphics. He has served for over 20 years in application engineering, marketing and management roles in the EDA industry, and has held IC design and design management positions at STMicrolectronics, Cadence, and Micron, among others. Jean-Marie holds a Master’s degree in Electrical Engineering from I.S.E.N Electronic Engineering School in Lille, France.

Jean-Marie Brunet, Marketing Director (Emulation Division), Mentor Graphics
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