Embedded software-driven hardware verification

June 1, 2010 OpenSystems Media

Another set of System-on-Chip verification methods relies on the execution of actual software on hardware using proven silicon, virtual prototypes of new and untested (and maybe not yet available) silicon, and FPGA prototypes. Sometimes all three methods are used, as we see in this perspective.

By best estimates, the software development effort behind 90 nm chip designs has already surpassed the hardware development effort. The projection for 2011 is that less than 40 percent of the overall chip development cost will be spent on hardware. Software now dominates project cycles and determines when a chip can get into volume production. As a result, the importance of software verification has increased, and software has taken on an integral role in the hardware verification process.

Bringing hardware and software together

Today, engineers use three basic techniques to execute software on a hardware representation. In derivative designs, portions of the software can be developed using the previous-generation chip. This approach often works best for the portions of the software that are higher up in a layered software architecture, specifically for hardware-independent applications.

Virtual prototypes offer the earliest solution in the design cycle because they can be implemented as soon as the architecture has been determined. These prototypes are pre-Register Transfer Level (RTL), register-accurate, and fully functional software models of the System-on-Chip (SoC), board, I/O, and user interfaces. They execute unmodified production code and run close to real time with external interfaces like USB as virtual I/O.

Because virtual prototypes are fundamentally software, they provide high system visibility and control, including multicore debug. They can also serve as a vehicle for collaboration between semiconductor and system houses. Since the standardization of the Open SystemC Initiative Transaction Level Model (TLM) 2.0 APIs, SystemC has become the suitable infrastructure to develop fast virtual prototypes using interoperable transaction-level models.

After the RTL is complete and has reached a stable state using functional verification techniques, FPGA prototypes can be used. The prototypes are a pre-silicon, fully functional hardware representation of the SoC, board, and I/O implementing unmodified ASIC RTL code. Optimally implemented, they can run at almost real time with external interfaces and stimulus connected, and provide, in conjunction with RTL simulation, higher system visibility and control than the actual silicon. FPGA prototypes offer significantly higher-speed levels than traditional hardware/software coverification, which combines RTL simulation with cycle-accurate processor models.

Depending on the required accuracy, speed, and desired time of availability, different technologies offer the most appropriate solution for software development and software-driven hardware verification. Hybrid offerings often allow designers to capitalize on the advantages of several offerings. For example, RTL simulation can be augmented with fast transaction-level models of processors and peripherals to increase simulation speed and verification coverage. Alternatively, virtual prototypes and FPGA prototypes that handle design problems in hybrid use modes, which combine software- and hardware-based execution, provide better solutions than the individual offerings.

Learning from real projects

To get a better grasp on the problem, Synopsys and International Business Strategies analyzed the project efforts and elapsed time of 12 projects that included complex hardware and software. Figure 1 shows an example of the 12 projects analyzed. The upper portion shows the timeline of the different development phases; the bottom portion shows the percentage of overall project effort for each of these phases.

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Figure 1: In an analysis of 12 projects, RTL verification used up 21 percent of the hardware/software development effort.

RTL verification averaged 21 percent of the overall hardware/software effort, or 38 percent of the hardware effort alone. In addition, RTL verification consumed about 55 percent of the elapsed time from requirements to GDSII. Verification continues throughout the flow toward tape-out in different variations, and the large percentage of effort spent on IP qualification can be considered another form of verification as well. Hence, verification easily reaches the often-mentioned 70 percent figure as a percentage of hardware development.

Looking at the development time for hardware from specification to tape-out, it took on average about a third of that time to port the OS, about one-half of that time to develop the utility software, and two-thirds of that time to develop the application software. A fully serial development process in which software development starts when engineering samples are available would have added another half to three quarters of a year to the project schedule. Unless the projects are being developed in parallel, software development delays the ability to ship hardware in volume.

While a stable specification – the prerequisite for virtual prototypes – is available 17 percent of the time from requirements to tape-out after project start, it takes almost 70 percent of the time from requirements to tape-out to arrive at stable RTL – the prerequisite for hardware prototypes. Virtual and hardware prototypes are available at very different times and therefore are applicable to very different development phases.

Enhancing verification efficiency

If a virtual prototype is made available early in the SoC design cycle for software development, it can evolve to meet different needs. Three main use models of software-driven verification utilize the integration of virtual prototypes with signal-level simulation at the RTL:

1.  When an RTL block becomes available, it can replace its TLM in the virtual prototype. Software can then be verified on this version of the prototype as a way to validate both hardware and software. Knowing that real system scenarios are used increases verification confidence. Furthermore, given that as much of the system as possible is simulated at the transaction level, simulation for verification is faster.

2.  The virtual prototype can also provide a head-start toward RTL verification test bench development and post-silicon validation tests by acting as a test bench component running actual system software. The virtual prototype can be used to generate system stimuli to test RTL and then verify that the virtual prototype and RTL function in the same way. Users can efficiently develop on the TLM embedded directed software tests, which can also be used for system integration testing. As a result, verification test case development productivity increases.

3.  As portions of the virtual prototype are verified as equivalent to their corresponding RTL, the virtual prototype can become a reference-executable specification. Consequently, users gain a single golden test bench for the transaction level and the RTL.

Figure 2 illustrates a USB On-The-Go example in the Synopsys Innovator virtual prototype development environment and a USB verification environment using transaction-level processor models and embedded software, respectively.

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Figure 2: In a USB verification environment, transaction-level processor models connect to RTL via USB.

Even when a virtual prototype is not available at the beginning of a project, the virtualization of hardware components can help incrementally increase verification efficiency starting from an RTL verification environment.

Replacing the RTL representation of on-chip processors in the system with virtual processor models at the transaction level can significantly increase simulation speed, which in turn shortens verification turnaround time. In several customer examples, replacing a single processor model boosted simulation speed up to 32x.

For incorporating software drivers in functional RTL verification to execute real product test cases, only the appropriate subsystem needs to be modeled and connected to RTL simulation. This can be as easy as adding a transaction-level processor model from a library, connecting it via a simple bus model to the TLM of the peripheral under verification, and connecting that to RTL, as shown in Figure 2.

Hybrid prototypes

To further boost verification efficiency by increasing simulation speed and the execution of the embedded software in the system, hardware prototypes can be used. Given that virtual prototypes and hardware prototypes are available at fundamentally different stages of a project, hybrid prototypes provide a viable solution that lets developers capitalize on the advantages of both worlds.

While virtual prototypes are available very early in the design flow – often only weeks after the specification has stabilized – they typically do not represent the full implementation detail that FPGA prototypes can expose. In contrast, FPGA prototypes run fully accurate at fairly high levels of speed, but are available later in the design flow, though still long before silicon returns from production.

A principal diagram of a hybrid TLM and hardware prototype is illustrated in Figure 3. Several hybrid use models combine the advantages of virtual prototypes and FPGA prototypes, including reuse of the actual RTL instead of remodeling and accelerating overall execution of hardware and software together.

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Figure 3: A hybrid use model of a virtual prototype and an FPGA prototype combines the advantages of both virtual and FPGA prototypes.

Smarter verification ahead

Due to the increasing influence that verification has on project efforts and timelines and that software has on project success, smart verification that takes into account embedded software is becoming more and more important.

Using virtual prototypes, verification efficiency can be incrementally improved both from the bottom up for RTL verification as well as from the top down starting with virtual prototypes. Incremental verification efficiency is achieved by augmenting traditional RTL simulation with virtualized transaction-level models of processors and peripherals. This increases the speed of simulation and allows direct execution of TLM reference models as part of the test bench. In top-down flows, verification efficiency can be increased by reusing existing virtual prototypes and their models, which can provide a head-start for verification scenario development by simply replacing the RTL under verification with a TLM until RTL is available. The virtual prototype then becomes a reference for RTL verification to follow.

Hybrids of virtual prototypes and FPGA prototypes as well as hybrids of RTL simulation and transaction-level models allow developers to capitalize on the combined advantages of the individual solutions. The immediate effect on verification efficiency largely stems from faster execution of simulations, which in turn enables faster verification turnaround.

Frank Schirrmeister is director of product management at Synopsys, where he is responsible for managing system-level products for virtual prototyping, architecture design, and processor development. Prior to joining Synopsys, Frank held senior management positions at Imperas, ChipVision, Cadence, AXYS Design Automation, and SICAN Microelectronics.

Synopsys
650-584-5000
www.synopsys.com

Frank Schirrmeister (Synopsys)
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