Designing cool, energy-efficient mobile devices

March 1, 2014 OpenSystems Media

Mobile devices increasingly require more performance out of less power, and run on processors that are gaining in complexity – with upwards of 100 IP blocks and counting on a single chip. These constraints and complexities will only increase as the industry develops the next generation of smartphones and other mobile devices, creating more of a challenge for system designers to optimize energy efficiency and performance in a short time to market timeframe. The Arizona State University Center for Embedded Systems (CES) is working on several projects that address these power issues.

Sarma Vrudhula, Professor at ASU says energy consumption should be the top focus of computer development.

“Energy efficiency is the central and first order metric that needs to be optimized,” Vrudhula says. The goal is to maximize performance subject to constraints of power consumption, while keeping heat – another big problem for small, contained mobile devices – under control.

“Performance and temperature and power consumption are tied,” Vrudhula says. “When a chip runs very fast it consumes a lot of power, which is dissipated as heat and causes the temperature to increase. This can affect the reliability of circuits, performance, reduce the lifetime of chips, and cause automatic shut down. You can try to maximize long-term reliability by running as cool as possible, but you can’t run [the processor] too cool because it runs too slowly; you have to also meet deadlines.”

Keeping power and heat under control with good directions

To address these power, performance, and heat issues, one of Vrudhula’s areas of research is based on dynamically controlling the speed of every processor core at runtime. With Intel processor boards, Vrudhula was able to demonstrate as much as 30 percent improvement in energy efficiency with a dynamic controller program. The software, which can be embedded in Linux, controls voltages and frequency of individual cores, and ensures the tasks are allocated appropriately to maximize energy efficiency.

This year, Vrudhula’s research focuses on expanding the dynamic control of multicore processors to SoCs. The research team will first study the relational effects of thermal properties, power, and performance of the SoC on each processing element and communication interconnect between elements; then create models based on the relationships; and, lastly, create an algorithm for optimization of these elements.

Architecting efficient low-power processor networks

CES research has also created a Network-on-Chip (NoC) tool chain for developing NoC architecture for future processors, a project led by ASU Professor Karam Chatha. The performance of multicore mobile processors is in large part determined by the on-chip interconnection architecture that links the IP blocks, referred to as an NoC communication subsystem. This NoC tool chain generates a high-performance, low-power on-chip interconnection architecture to address multiple design requirements, taking a task that would normally involve several weeks of manual effort down to minutes. Requirements such as multiple traffic classes, multiple use-cases, deadlock avoidance, multiple clock islands, bit-width optimization, and router arity constraints can be addressed and optimized. The resulting synthesized mobile processor interconnection architecture is able to get better performance and lower power consumption in a shorter timeframe.

Managing mobile power with efficient communication

ASU Assistant Professor Carole-Jean Wu is currently working on a research project based on achieving energy-efficient mobile computing with data communication and global power management. The project aims to design an energy-efficient mobile architecture that takes into account user behavior and the “cost” of data communication between hardware components to allow the processor to “wake up” less frequently for data coordination. Wu’s approach is to develop a model of the microarchitecture-level power and energy characterization based on user patterns, and then design an efficient smartphone architecture using global power management that minimizes data movement frequency and distance with an efficient memory hierarchy.

Designing efficient mobile systems

Research into energy-efficient design continues to be an important area for CES member companies and staff, as power constraints affect the capabilities of every system. Vrudhula cited the human brain as a model of energy efficiency, with computers falling around 10-12 orders of magnitude behind in efficiency. In time, research may be able bridge that gap – or at least help our smartphone batteries last longer than a day.

For more information about the CES visit ces.asu.edu

Monique DeVoe (Managing Editor)
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