Verification and Validation Are the Same Yet Very Different

May 15, 2018 Anupam Bakshi, Founder and CEO, Agnisys

In 2011, Intel discovered a design flaw in its Sandy Bridge combination graphics-microprocessor chip that led to not only a major production delay, but that ultimately cost more than $1 billion in replacement costs and lost revenue. If you're searching for a clear-cut example as to why finding bugs early in the development process is always a top priority, look no farther than that. A product recall can be a terrible experience for everyone involved, but the costs associated with that recall alone are the stuff that nightmares are made of.

At the same time, the complexity of the modern SoC environment has made things difficult in this regard to say the least. Getting a SoC to market is such an enormous task that teams are always looking for newer and more innovative ways to shorten the development time. The situation has also raised the requirement to incorporate verification and validation as a one-step process to catch bugs from an early design stage. Bringing the enormous tasks of verification and validation closer together is great news for semiconductor industry.

This, however, is where the concept of "shift left" enters the conversation. As its name suggests, "shift left" is a series of activities and processes that better position design teams to anticipate and address downstream issues upfront, thus fixing a small problem now before it becomes a much bigger (and more expensive one) tomorrow. It's the heart of the idea that you should "test early and often." It also does so in a way that has proven to shorten development times so that no time is wasted late in the process where every second counts.

Why This Matters

Before we can focus on the importance of "shift left," we must first address the early stages of this process in general. Verification and Validation are two critical steps in the creation of electronic systems, but over the last few years their roles (and how those roles relate to one another) have changed.

In the modern era, there’s an urgent need to enable users to describe a device’s programming and test sequences in a way that automatically generates sequences ready to use from an early design and verification stage, all the way up through post-silicon validation. Using the principles at the heart of "shift left," this process can now be combined into a single-step process using just a portable sequence generator for verification, firmware, and validation all at the same time. ISequenceSpec is one example of such a tool, which is intended to help design teams generate both the unified UVM sequences necessary from the specification to both catch bugs early and often and increase the ability to collaborate and communicate across teams.

Thanks to solutions like ISequenceSpec, we’re now seeing a major opportunity to end the perception that verification and validation are separate tasks for the majority of chips now being created. The fact that engineers can write a single sequence spec, generate UVM sequences for verification, Verilog sequences for validation AND various output formats for Automatic Test Equipment is a massive time saver to say the least.

One major benefit of a single specification format is that a deeper level of synchronization is now a guarantee between various disparate stages of the development, from verification to post-silicon validation and everything in between. Not only are these test sequences automatically generated (freeing up engineering resources to focus their efforts elsewhere), but it also provides invaluable insight that can be leveraged to fine-tune performance and to better understand complicated hardware/software interactions at a deeper level than ever before.

On top of all of this, available tools are generally very straightforward. The entire process is often completed using the register information for important standard formats like IP-XACT, SystemRDL, and XML. Users can define the necessary test sequences in a simple editor, then generate the unified test sequences that would enhance the overall efficiency of the process and the end result.

As technology continues its rapid evolution, our perspective on SoCs must evolve with it, particularly when it comes to verification and validation. Make no mistake: these are not two separate concepts anymore and in truth, they haven't been for quite some time. They're simply two sides of the same coin. Creating a one specification format therefore becomes a way to guarantee synchronization between the various stages of the process, thus preserving the integrity of the finished product.

Anupam Bakshi is the founder and CEO at Agnisys. He has more than two decades of experience implementing a wide range of products and services in the High-Tech industry. Prior to forming Agnisys, he held various management and technical lead roles at companies such as Avid Technology, PictureTel, and Cadence. Anupam earned an MBA and an MS in Computer Engineering from Northeastern University and a MS in Electronics from Delhi University.

Previous Article
Using a memory protection unit with an RTOS, part 2
Using a memory protection unit with an RTOS, part 2

Introduced in 2004, the ARM Cortex-M architecture is currently the most popular 32-bit architecture on the ...

Next Article
Five Minutes with…Yannick Moy, Sr. Software Engineer, AdaCore
Five Minutes with…Yannick Moy, Sr. Software Engineer, AdaCore

Software insecurities are badly addressed by current “best practices.” Those are the words of this week’s F...

×

Stay updated on Developer Tools & Operating Systems with the Dev Tools and OS edition of our Embedded Daily newsletter

Subscribed! Look for 1st copy soon.
Error - something went wrong!