I took a couple weeks and thought about the ideas that got tossed around in my head at the 47th Design Automation Conference in Anaheim. I enjoyed the trip a lot – six hours of drive with tunes both ways, fireworks, dinners, burger at Knowlwood – and the discussions at the show got me thinking.

There were several things that jumped out at me. The first is that nobody can afford an SoC mistake any more. People will tell you that the cost of developing a top-of-line SoC is somewhere between $2M and $10M depending on how good their value-based accounting system is. Let’s take our friends at say, Apple. The A4 chip is in both the iPad and the iPhone 4. It’s the same part, according to independent teardown data from Chipworks. Do you think the “death grip” antenna location in the iPhone 4 has anything to do with the fact the pinout of the part didn’t change (apply what you know about mixed signal design and PCB layout before saying “no way”)? Do you think the designers of the iPad took that into account when they spec’d out the A4? I’m just speculating here, but I’ve seen the movie and I can tell you once the A4 was working and had stable software and tools, the pressure was huge to reuse it and get the volumes up – and the iPhone 4 designers had to live with it, pinouts and all. It seems if the antenna could have been put somewhere else, it would have been … just saying, would enjoy comments on that theory.

Our friends at ARM are intensely worried about another situation vis a vis the investments their customers are making. A funny thing can happen when you take really fast IP blocks – like, maybe an Eagle processor core at 2 GHz – and connect it to other stuff. A completely happy processor core that was thoroughly tested can suddenly be shredded by some side effect coming from another IP block. I can tell you ARM is going to great lengths to “play customer” and working with the EDA[] vendors to develop tools and methods to expose, troubleshoot, and hopefully eliminate any issues – but the stakes are high here. This is one reason our friends at Intel have kept their chipset closed, exposing only the PCIe interface – it saves them a bunch of potential headaches. ARM is taking this head on, kudos to them, and it’ll result in better core IP, better EDA tools, and higher performance SoCs when they’re done.

I also heard a lot of talk about the “non-production (fill in the blank) tool”. The big guys own the back end process along with the foundries, and those tools do a fantastic job – but they can take a long time to run. It’s a bummer when you make an overnight (or longer) run and find out something isn’t quite right. There are a lot of vendors making various tools to help get answers in perhaps 20 minutes so a designer can be headed down the right path, or know they definitely aren’t. (Spock to Kirk: “If we go by the book, hours would seem like days.” I hope they keep that line in the next installment.) Again, it’s about reducing the cost of the design and making sure when the result comes out the other end, it’s right. The folks at Atrenta (”early closure”) and Real Intent (”early functional verification”) had a couple of the more interesting stories in this vein.

In: High-level design. Out: ESL. One law in marketing is when you ask 20 people about a term and they give you 20 different definitions, it’s time for a new term. ESL suffers from that – nobody can tell you what it means. All the votes I got were for high-level design, which still means quite a few things but generally translates to something beyond just RTL. You’ll see a lot of ideas in our June issue of Embedded Computing Design, and there are a lot more out there. Oasys Design Systems and Forte Design Systems have some good ideas here, and the Cadence, Mentor Graphics, Synopsys camp does too.

Speaking of that camp (who were all gracious to me, thank you), it’s oddly intriguing to see technical leaders from all three of those companies sitting right next to each other (along with Freescale, Intel, and Xilinx) during a panel at the Accellera breakfast discussing OVM 1.0 EA and the near term 1.0 release. Early during the standards process, at some point competitors and customers have to lock arms and say “we’re all behind this,” and egos and technological purism have to be put mostly in the background (I said mostly, there were a couple interesting moments). Two years from now, when OVM has traction, they’ll be back to competitive mode, but it’s nice to see them working together, and the result will again be better tools.

There’s also concern over tool flow, especially in the disparity between analog[]/mixed-signal and digital tools, and there’s folks like Magma DA and Tanner EDA trying to solve that one so designers can be more productive.

Verification is increasingly hot – everyone apparently wants it, back to the $2M to $10M problem – and Aldec, EVE, Magma DA, SpringSoft, and others are working on that.

Shortly we hope to have details on an EDA Virtual Conference where you can learn more about many of these topics, stay tuned. All in all a fun trip, learned a lot, met a lot of great folks, and looking forward to bringing you more information on how SoCs, software, and EDA continue to converge.