Tricks for fixing troublesome PCIe links

When debugging a PCIe channel that shows no signs of linking, designers can take several steps to remedy this problem. First, confirm that neither device at each end of the link is stuck in reset. Next, probe signal lines and ensure that they are the proper level. Also, check if a reference clock is supplied to both devices and connected as prescribed by the data sheet. Non-spread spectrum clocks must be within the PCIe limit of ±300 ppm. If spread spectrum clocking is employed, it must be properly down-spread, and the two systems must operate from a common clock.

Another step is to check for incorrect or cracked link bypass capacitors, ensuring that the capacitors are 75 to 200 nF and unbroken. A link’s inner and outermost lanes are the most important lanes to verify. For a multilane link, PCIe protocol allows for automatic down-train negotiation to the highest or lowest lane. Reduce the link width to x1 and check for linkup. If register access or link separation is not possible, remove the bypass capacitors from the remaining links.

Reducing signal speed takes one variable out of the equation. Though it is rare, some Gen 1 devices behave incorrectly when connected to a Gen 2 device. To address these rogue endpoints, PCIe device vendors often include special features that enable a Gen 2 switch to revert speed and autonegotiate capabilities back to Gen 1 defaults.

If there’s still no link after these steps are taken, that means channel distance could be posing a problem. When operating at long distances (15" to 20" or longer), PCIe Gen 2-capable devices can cycle between Gen 1 and Gen 2 speed negotiations if the channel equalization settings are poor and there is no higher-level supervisor or system timer to limit retries. If the link is 15" or longer, changing receiver equalization levels and/or transmitter emphasis could be effective.

An additional step is to check the device-specific registers for the ability to mask receiver detection. Ignoring receiver detection allows the set device to immediately transmit the link training protocol. If one end of the link is incorrectly sending a compliance pattern, sending the training sequence into the Rx will initiate the proper link handshake protocol.

If these steps don’t work, it might be necessary to put a link protocol analyzer between the two nonlinking devices. In the absence of such an analyzer, an internal debug probe in some PCIe switches can track link states, perform basic triggers, and provide valuable chip and link status.

Partial linkup

If the system links at Gen 1 but not Gen 2 because of equalization for longer links, marginal system clocks, and legacy protocol errors, try increasing channel equalization. Confirming that the clock source being used meets Gen 2 jitter requirements can also resolve this issue. Even for Gen 2, linkup is first required at Gen 1 speeds, so failure to operate at Gen 2 is often the result of channel quality and the need for equalization. Given this fact, designers should:

• Ensure that both ends of the link are Gen 2 capable
• Confirm that the PCIe reference clock is within jitter specification
• Check if forcing Gen 1 speeds allows a solid link
• Test device-specific registers for the ability to lower the electrical idle threshold and adjust as necessary
• If the link is 10" to 15" or more, adjust Rx and Tx equalization (see Figures 1 and 2)

Figure 1: A receiver Rx signal rebuffered to scope before equalization

Figure 2: An Rx signal after equalization adjustment (click graphic to zoom by 1.9x)

Finally, designers should doublecheck errata sheets; the answers might be out there.

Reginald Conley is director of applications at PLX Technology, based in Sunnyvale, California. He holds an MSEE and an MBA from San Jose State University.

PLX Technology rconley@plxtech.com 408-328-3500 www.plxtech.com