Hybrid DSP From CEVA Adds Controller Functionality

January 4, 2019 Rich Nass

Many IoT applications, particularly those serving consumer, automotive, and industrial markets require both digital signal processing (DSP) capability, as well as digital signal control. The DSP part is to handle things like noise reduction and speech recognition, while digital signal control is used for PHY and motor control, as well as sensor-fusion.

Having all that logic in one device would be an advantage, and that is what’s offered by the CEVA-BX hybrid DSP-controller. CEVA, a licensor of signal processing platforms and AI processors, has developed this part aimed specifically at voice, video, communication, sensing, and digital signal control applications.

The CEVA-BX combines low power with the high-level programming and compact code size requirements of a large control code base. Using an 11-stage pipeline and a five-way VLIW micro-architecture, it offers parallel processing with dual scalar compute engines, load/store and program control that reaches a speed of 2 GHz using common standard cells and memory compilers. The part’s instruction-set architecture (ISA) supports single-instruction, multiple-data (SIMD), common in neural network inference, noise reduction, and echo cancellation, as well as half-, single-, and double-precision floating-point units for high accuracy sensor fusion and positioning algorithms.

The CEVA-BX is initially offered in two configurations: the BX1 with one 32- by 32-bit MAC and quad 16- by 16-bit MACs, and the BX2 with quad 32- by 32-bit MACs and octal 16- by 16-bit MACs. The BX2 can handle intensive workloads like 5G PHY control, multi-microphone beamforming, and neural networks for speech recognition, with up to 16 GMACs/x. The BX1 serves low to mid-range applications, such as cellular IoT, protocol stacks, and always-on sensor fusion, with up to 8 GMACs/s. Security is addressed using dedicated trusted execution modes.

The family is accompanied by a software development tool chain, including an LLVM compiler, Eclipse-based debugger, DSP and neural-network compute libraries. The cores are available now to lead customers and by end of Q1/2019 for general licensing.

About the Author

Rich Nass

Richard Nass is the Executive Vice-President of OpenSystems Media. His key responsibilities include setting the direction for all aspects of OpenSystems Media’s Embedded and IoT product portfolios, including web sites, e-newsletters, print and digital magazines, and various other digital and print activities. He was instrumental in developing the company's on-line educational portal, Embedded University. Previously, Nass was the Brand Director for UBM’s award-winning Design News property. Prior to that, he led the content team for UBM Canon’s Medical Devices Group, as well all custom properties and events in the U.S., Europe, and Asia. Nass has been in the engineering OEM industry for more than 25 years. In prior stints, he led the Content Team at EE Times, handling the Embedded and Custom groups and the TechOnline DesignLine network of design engineering web sites. Nass holds a BSEE degree from the New Jersey Institute of Technology.

Follow on Twitter Follow on Linkedin Visit Website More Content by Rich Nass
Previous Article
Avnet and Newark element14 Join Forces on SmartEdge Agile with AI and Security at the Edge

Newark element14 and Avnet, along with Octonion and ST Microelectronics, have developed SmartEdge Agile, a ...

Next Article
Beyond Sensors and Cameras - Moving the IoT off the Cloud and into the Physical World

Embedded motion control devices have begun to enable development of smart, secure, low-cost motorized produ...