Advanced functional verification and debug of PCI Express-based designs

Functional verification of PCI Express logic cores requires significant investment to develop and maintain a layered test bench environment.

By Chris Browy
August 13th, 2006

Full Text: Download PDF

Feature / Discussion: 2006-08-13Verification Intellectual Property (VIP) streamlines the path to compliance sign-off through a reusable, layered verification methodology supported by highly configurable and feature-rich transactors, protocol assertions, advanced debug support, and comprehensive functional and compliance checklist test suites. Chris considers the role of VIP for core- and chip-level verification of PCI Express-based designs to ensure robust device-level and interface compliance.

Topics covered in this article

Home > Articles > Chris Browy

More from this issue:

What's popular:

Comments:

Silicon, software, and strategies for embedded devices
Embedded Computing Design magazine is the resource for engineers, architects, and decision makers involved with embedded devices. Topics explored span silicon, software, and strategies for designing and connecting with small devices in mobile, automotive, home, industrial, and medical applications. Departments include Deep Green discussing the latest in energy efficient, low power designs and applications. Content is available in print, E-letter, E-cast, white papers, video, RSS, social networks, and more. Subscriptions are free of charge.
©MMXIIEmbedded Computing Design.
An OpenSystems Media publication.