Flexibility to program gates, low power consumption, and design simplicity generally haven’t gone together very well. The newest PSoC 3 and PSoC 5 families are implementing an approach to try to change that. Palani describes specific measures that can be taken to cut power in a programmable device.
Embedded designers today are facing more and more pressure to increase battery life and at the same time offer more features. One only needs to look at the rapid increase of functionality in mobile handhelds for verification of this trend. It has become clear that battery chemistries are not improving at the rate needed to fulfill these requirements. This places the pressure squarely on silicon vendors to deliver better performance at lower power. As if this dilemma wasn’t challenging enough, designers face strict time-to-market requirements posed by shrinking design cycles.
Apart from lower current consumption, there is also a need to lower system voltage. A few years ago, the standard for minimum operating voltage was 3.3 V. Today, it is 1.8 V. Charting this trend, it is realistic to project a subvolt operating range for tomorrow’s devices. This opens up the ability to build System-on-Chip (SoC)-based designs with a single AA or AAA battery, whose end-of-life voltage is roughly 0.9 V.
Although some SoC-based designs can run at 1.8 V today, analog[
] performance often degrades with such low voltages. For handheld, battery-powered designs that require good analog performance and operation below 1 V while still meeting analog performance requirements, the solution is offering the ability to move to a single AA or AAA battery. This translates to lower cost for the consumer and fewer batteries.
Accomplishing subvolt operation
Subvolt operation can be achieved when the embedded SoC device has a built-in boost converter that can boost the input voltage (such as 0.5 V) to a higher system-level voltage (the aforementioned 3.3 V or 5 V). In this mode, it is important that the noise from the boost converter does not affect the performance of analog peripherals. Figure 1 shows the system-level connections for an integrated boost converter that is part of a PSoC 3 programmable SoC from Cypress Semiconductor.
The PSoC 3 and PSoC 5 families are field-programmable embedded SoCs with programmable digital blocks and configurable analog blocks. These devices are designed to offer flexibility and programmability while consuming very low sleep and active current. The architectures also offer analog performance with 16- to 20-bit precision. The families are supported by PSoC Creator software, an integrated development environment that can be used to rapidly develop designs from end to end, all the way from device selection, configuring/programming the digital and analog peripherals, configuring the power system, firmware development, debug, and programming.
Having an integrated boost converter that can accept subvolt input voltages has advantages, as it paves the way for running the system from a single AA or AAA battery (or even low-voltage sources like solar cells). It also provides a guaranteed minimum system voltage even with a varying supply voltage. Finally, the boost output voltage can run other circuitry in the system that needs higher voltage, like an LCD screen or sensors.
Wide supply voltage range
Having a wide supply voltage range that spans from 1.8 V (0.5 V with boost enabled) to 5.5 V provides maximum flexibility because of the following reasons:
· It can span standard battery voltage ranges for most common batteries through their end-of-life voltage, as shown in Figure 2.
· It provides compatibility with legacy system voltages of 3.3 V and 5 V.
· The upper end of 5.5 V provides a margin above 5 V for rail-to-rail measurements of signals from legacy systems.
Offering a wide external supply voltage while maintaining a low, stable core voltage for silicon can be accomplished by providing built-in low-dropout regulators within the device. Moreover, having separate internal regulators for digital and analog domains ensures that analog performance is not compromised due to noise from the digital power rails. Figure 3 shows the system-level connections and internal regulators that accommodate a wide supply voltage range.
In Figure 3, Vddd and Vdda can vary from 1.71 V to 5.5 V while the built-in analog and digital regulator ensures that the core still runs at a stable low voltage. When properly designed, this system also ensures the same analog performance across the entire supply voltage range.
To allow interfacing to other devices in the system that might have different system voltages, an SoC needs separate I/O power rails that can be independently set to any voltage within a wide voltage range. An SoC that has four I/O banks, with each I/O bank able to be driven by any voltage from 1.8 V to 5 V, provides seamless interfacing to other devices on a board, as shown in Figure 4.
Flexible power modes
While the myth that programmable systems are power hungry persists, well thought-out programmable SoCs can have world-class power numbers that match those of stand-alone MCUs. The power modes that are desirable in an end customer’s application and their corresponding power numbers are shown in Figure 5.
Active mode is the system’s normal operation mode when the user is actively using it. A programmable SoC provides the capability to selectively disable unwanted peripherals in this mode.
In Alternate Active mode, fewer peripherals are active. This provides a reduced-power Active mode that can be entered from the regular Active mode. Upon exit from this mode, the system returns to regular Active mode. An example use case for this is a situation wherein an embedded system with a display continues to operate while the display alone is turned off. When the display needs to be turned off, the system will enter Alternate Active, in which case the peripherals needed for the display are turned off.
Sleep is a commonly used mode in battery-powered embedded systems. This is an extremely low-power mode, in which all peripherals are in a low-power state while a real-time clock can be maintained. This mode is also used for systems that need constant duty cycles between Active and Sleep. An example use case is a temperature sensor that needs to update its readings every minute. The system wakes up every minute, takes the reading, and goes back to sleep. This results in reduced average power.
Hibernate is the device’s lowest power consumption mode while memory contents and configuration can still be maintained. The ability to wake up from an I/O source allows the user or another device in the system to wake the device up. Hibernate mode can also be used to eliminate a power switch in a handheld device because the device can wake up on any button press.
Low power with programmability
A programmable SoC offers high levels of integration and provides the ability for users to build their own custom peripherals using a highly configurable and programmable system. Carefully designed programmable SoCs can offer world-class power management features that not only meet MCU power numbers, but also offer a configurable power management system and deliver precise analog performance.
Palani Subbiah works as a systems engineering manager in the Consumer and Computation Division at Cypress Semiconductor, based in San Jose, California. He holds a Bachelor’s of Engineering in Electronics and Communication Engineering from Sri Venkateswara College of Engineering and an MSEE from the Missouri University of Science and Technology.
Cypress Semiconductor
408-943-2600
www.cypress.com
